Minimizing Surface Dielectric Loss in Superconducting Devices

In the race to build a quantum computer, the transmon qubit has become a leading technology in the field. Achieving a high quality factor and long relaxation time are important in enabling realistic quantum computing. A large source of decoherence can be attributed to dielectric loss largely confined to the surfaces and metal edges of superconducting devices. Past studies of capacitor pad and junction geometries in 2D planar qubits have worked to study and minimize the electric field participation in these lossy regions. 

In this work, we consider alternative device geometries which may further reduce surface dielectric loss - specifically flip-chip geometries (flipmons). This structure has been chosen in particular because it increases the electric field concentration in the vacuum region where there is inherently no loss. We explore the loss of these structures and compare them to more traditional 2D geometries. Our results have implications for designs and packaging of multi-qubit devices as well as loss-low superconducting devices.