Department of Electrical and Systems Engineering, University of Pennsylvania, Philadelphia, PA 19104, USA

In recent years, silicon spin qubits have emerged as a viable contender for scalable quantum computing, demonstrating high single and two-qubit gate fidelities, as independently reported by multiple research groups [1-3]. The numbers reported, in conjunction with various scaling schemes proposed, present a picture that achieving fault tolerance with silicon quantum processors may be plausible. In this presentation, we describe a four-qubit quantum processor fabricated at the University of Pennsylvania based on designs reported in the past [4]. We outline our quantum control setup meticulously tailored to quantum dot experiments. Preliminary device performance metrics will be reported and discussed.

[1] Xue et al., Nature. 601, 343 (2022)

[2] Noiri et al., Nature. 601, 338 (2022)

[3] Mills et al., Sci. Adv. 8, eabn5130 (2022)

[4] Sigillito et al., Phys. Rev. Appl. 11, 061006 (2019)