Bulletin of the American Physical Society
APS March Meeting 2021
Volume 66, Number 1
Monday–Friday, March 15–19, 2021; Virtual; Time Zone: Central Daylight Time, USA
Session A30: Quantum Computing Architectures IFocus Live
|
Hide Abstracts |
Sponsoring Units: DQI Chair: Andrei Vrajitoarea, Princeton University |
Monday, March 15, 2021 8:00AM - 8:12AM Live |
A30.00001: A quantum state router based on parametrically driven photon exchange. Chao Zhou, Pinlei Lu, Mingkang Xia, Tzu-Chiao Chien, Xi Cao, Ryan Kaufman, Roger Mong, David Pekker, Michael Jonathan Hatridge Precisely controlled couplings between qubits are a vital part of all quantum information processing. For superconducting qubits, most efforts seek to implement a “surface code” architecture, which only couples nearest-neighbor qubits. However, longer range couplings are very desirable as they reduce the overhead of interactions between distant qubits. We present a design that can realize long range couplings between qubits through a modular quantum router. The design contains a 3D superconducting waveguide ‘trunk’ of microwave modes and a Superconducting Nonlinear Asymmetric Inductive eLement (SNAIL) to generate parametric photon exchange couplings between each pair of modes. We couple individual modules via a communication cavity deliberately detuned from a corresponding waveguide mode. Quantum information is exchanged between modules by driving the SNAIL at the difference of the communication modes’ frequencies. We will present experimental results on fast all-to-all coherent photon SWAPs between arbitrary cavity pairs, as well as multiple, simultaneous SWAPs. We will also discuss our efforts to engineer longer mode lifetimes in the router and design filters to enable stronger pumping and faster SWAP gates. |
Monday, March 15, 2021 8:12AM - 8:24AM Live |
A30.00002: Cryogenic Characterization of Low-frequency Noise Based on Cryo-CMOS: Impact of Interface Trap Density Hiroshi Oka, Takashi Matsukawa, Kimihiko Kato, Shota Iizuka, Wataru Mizubayashi, Kazuhiko Endo, Tetsuji Yasuda, Takahiro Mori To enhance the performance of Si quantum computer, prolonged coherence-time of Si spin qubits is necessary. Recently, it has been revealed that the coherence-time of the Si spin qubit is limited by low-frequency noise related to charge fluctuations. However, the source of charge noise generated at cryogenic temperature has not been elucidated. This is because there are several possible noise sources in Si qubits depending on its structure, and it is hardly possible to identify the source by the qubit measurement as itself. Since Si qubits have the same basic structure as CMOS, it is natural to expect that Si qubits and cryo-CMOS have a common noise source. Thus, we proposed low-frequency noise analysis based on cryo-CMOS to understand the coherence-time limiting factor of Si qubits. For this purpose, we fabricated cryo-CMOS on various surface orientations, exhibiting different interface trap density, and experimentally clarified the correlation between the interface trap and the cryogenic noise. It was found that the cryogenic noise is determined by the amount of interface trap, which indicates that the fluctuation of carriers at interface trap states is an exclusive origin of charge noise in Si spin qubits. |
Monday, March 15, 2021 8:24AM - 8:36AM Live |
A30.00003: Mobility limiting factors in Si-MOSFETs fabricated with a full CMOS process Timothy Camenzind, Asser Elsayed, Bogdan Govoreanu, Stefan Kubicek, Iuliana Radu, Dominik Zumbuhl Silicon is one of the leading candidates for future spin- and valley-qubit applications. The performance of these qubits depends mostly on the interface quality, which depends on the fabrication process and the materials used. Here, we study the influence of various gate stacks on the density and mobility of both electrons and holes in Si-MOSFETs fabricated in a full CMOS process. Primarily, the material of the gate stack has the highest impact with peak mobilities ranging from 4’000 to 16’000 cm2/Vs. This is believed to be linked to the strain that the gate stack material exerts on the substrate, therefore influencing the quality of the interface. Various parameters such as the roughness of the interface and background impurity densities were directly extracted from mobility vs density curves, further enhancing the understanding of the mobility limiting factors in these types of devices (Kruithof et al., PRB 43 6642 (1991)). Additionally, from measurements down to millikelvin temperatures we were able to extract parameters such as the effective mass and quantum lifetimes of up to 2 ps. These results show the viability of a full CMOS process for qubit device fabrication. |
Monday, March 15, 2021 8:36AM - 8:48AM Live |
A30.00004: Employing CMOS technology on silicon for a scalable electron-spin qubit architecture Jan Klos, Bin Sun, Jacob Beyer, Sebastian Kindel, Lena Hellmich, Joachim Knoch, Lars Schreiber Electrostatically-defined quantum dots (QDs) in silicon are an attractive platform for quantum computation. We propose a scalable qubit device fabricated by industry-compatible processes. The device consists of two dense parallel arrays of QDs localized along a silicon nano-ridge. We implement side-gates and a global back-gate for confinement and a dense metallic top-gate structure for individual control. To minimize potential fluctuations caused by interface roughness and charged defects, the nano-ridge is bounded by atomically-flat {111} facets. According to electrostatic simulations, all QDs can be tuned individually including inter- and intra-array tunnel couplings ranging over multiple orders of magnitude. The most relevant process modules are demonstrated experimentally including anisotropic wet-etching, local oxidation and side-gate formation of the silicon nano-ridge and top-gate fabrication employing the self-aligned spacer process. SiO2 spacers of 10 nm width on a 50 nm pitch have been achieved. We characterized the atomic flatness of the etched {111} facets and the defect density exhibiting a low Si/SiO2 interface defect density of ~1010 V−1cm−2. |
Monday, March 15, 2021 8:48AM - 9:00AM Live |
A30.00005: Laser annealing for two-qubit gate error reduction in fixed frequency processor architectures Eric Zhang, Srikanth Srinivasan, Neereja Sundaresan, Daniela F Bogorin, Yves Martin, Jared B Hertzberg, John Timmerwilke, Emily Pritchett, Jeng-Bang Yau, Xinhui Wang, William Landers, Eric Lewandowski, Adinath Narasgond, Sami Rosenblatt, George Keefe, Isaac Lauer Lauer, Mary Beth Rothwell, Oliver E. Dial, Jason Orcutt, Markus Brink, Jerry Chow Fixed-frequency transmon qubits are attractive due to noise immunity and high coherence. However, as quantum processors are scaled, frequency crowding resulting from level degeneracies reduces two-qubit gate fidelity [1]. We implement a scalable laser-based frequency trimming technique that has been implemented on processors at the 65-qubit scale, enabling low-error gates with average fidelities approaching 99%. We discuss ultimate tuning precision of the method and its consequences for processor scaling. |
Monday, March 15, 2021 9:00AM - 9:12AM Live |
A30.00006: Universal Quantum Circuitry: High-Fidelity Deutsch Gate and Toffoli Gate Protocols Using GaAs/InAs Quantum Dots Paul Bailey, Jean-Francois S Van Huele We propose to incorporate two GaAs/InAs quantum dots in a larger circuit comprised of linear optical elements to create a spin-spin-photon polarization three-qubit Deutsch gate D(θ), where the parameter θ is tuned by rotating half-wave plates. Since the Deutsch gate is a universal quantum logic gate, a combination of Deutsch gates can complete any quantum computing task, a necessary condition for full-fledged quantum computing. Although Shi proposed to build a Deutsch gate using Rydberg blockade of neutral atoms [X-F Shi, Phys. Rev. Applied 9, 051001], no Deutsch gate has been experimentally realized so far. Our proposal offers another route toward a Deutsch gate realization using GaAs/InAs quantum dots. We display fidelity plots of our Deutsch gate protocol under realistic conditions for the GaAs/InAs quantum dots reporting fidelity values as high as 0.975. A single Deutsch gate can implement the much used Toffoli gate by operating at the appropriate angle, namely θ = π/2. We also identify a sub-circuit of our Deutsch gate circuit that yields a Toffoli gate protocol. We compare both Toffoli gate implementations—including their fidelity values—and highlight the advantages of the Deutsch gate protocol containing a sub-circuit Toffoli gate protocol. |
Monday, March 15, 2021 9:12AM - 9:24AM Live |
A30.00007: Implementing a fast unbounded quantum fanout gate using power-law interactions Andrew Guo, Abhinav Deshpande, Su-Kuan Chu, Zachary Eldredge, Przemyslaw Bienias, Dhruv Devulapalli, Yuan Su, Andrew Childs The standard circuit model for quantum computation presumes the ability to directly perform gates between arbitrary pairs of qubits, which is unlikely to be practical for large-scale experiments. Power-law interactions with strength decaying as 1/rα in the distance r provide an experimentally realizable resource for information processing, whilst still retaining long-range connectivity. We leverage the power of these interactions to implement a fast quantum fanout gate with an arbitrary number of targets. Our implementation allows the quantum Fourier transform (QFT) and Shor's algorithm to be performed on a D-dimensional lattice in time logarithmic in the number of qubits for interactions with α ≤ D. As a corollary, we show that power-law systems with α ≤ D are difficult to simulate classically even for short times, under a standard assumption that factoring is classically intractable. Complementarily, we develop a technique to give a general lower bound, linear in the size of the system, on the time required to implement the QFT and the fanout gate in systems that are constrained by a linear light cone. This allows us to prove an asymptotically tighter lower bound for long-range systems than is possible with previously available techniques. |
Monday, March 15, 2021 9:24AM - 9:36AM Live |
A30.00008: Scaling Law in Large Quantum Devices with Dissipation Shohei Watabe, Michael Serikow, Shiro Kawabata, Alexandre M Zagoskin Recently, the Google reported quantum supremacy using 53-qubits with Sycamore chip, the D-wave systems released "Advantage" 5000-qubits quantum annealing machine, and the IBM announced a roadmap of chips: Eagle with 127-qubits in 2021, Osprey with 433-qubits in 2022, and Condor with 1121-qubits in 2023. While large enough quantum systems have been developed and will be developed, the full description of quantum mechanics for such a large system cannot be simulated with classical computers, and the question naturally arises: how we test if it is capable of performing quantum computing? The answer may be given by a reduced description of qualitatively different regimes of behavior of such systems. In this talk, we present a statistical approach to such a description of large quantum systems. |
Monday, March 15, 2021 9:36AM - 10:12AM Live |
A30.00009: Micro-architecture of quantum information processor using planer packaging Invited Speaker: Hiroto Mukai Of the many potential hardware platforms, superconducting quantum circuits have become the leading contender for constructing a scalable quantum computing system. Not only have we seen significant advances in recent years in reliable fabrication and control technology, but the quality of the qubits themselves have increased by many orders of magnitude. Almost current architecture designs necessitate a two-dimensional arrangement of superconducting qubits with nearest-neighbor interactions, that is compatible with powerful quantum error-correction using the surface code. |
Monday, March 15, 2021 10:12AM - 10:24AM Live |
A30.00010: Efficient Hamiltonian programming in qubit arrays with nearest-neighbor couplings Takahiro Tsunoda, Gaurav Bhole, Stephen Jones, Jonathan Jones, Peter J Leek We consider the problem of selectively controlling couplings in a practical quantum processor with always-on Ising interactions that are diagonal in the computational basis, using sequences of local not gates. This methodology is well known in nuclear magnetic resonance implementations, but previous approaches do not scale efficiently for the general fully connected Hamiltonian, where the complexity of finding time-optimal solutions makes them only practical up to a few tens of qubits. Given the rapid growth in the number of qubits in cutting-edge quantum processors, it is of interest to investigate the applicability of this control scheme to much larger-scale systems with realistic restrictions on connectivity. Here we present an efficient scheme to find near time-optimal solutions that can be applied to engineered qubit arrays with local connectivity for any number of qubits, indicating the potential for practical quantum computing in such systems. We will discuss the application of this scheme in realistic devices. |
Monday, March 15, 2021 10:24AM - 10:36AM Live |
A30.00011: Development of the Quantum Scientific Computing Open User Testbed (QSCOUT) Christopher G Yale, Matthew G Blain, Raymond A Haltli, Craig Hogle, Andrew Landahl, Daniel Lobser, Jessica M Pehr, Melissa C Revelle, Brandon P Ruzic, Jay W Van Der Wall, Joshua Wilson, Susan M Clark The Quantum Scientific Computing Open User Testbed (QSCOUT) at Sandia National Laboratories is a quantum computing testbed based on trapped ions with the goal of providing low-level access to quantum hardware for scientific computing applications. Our system uses one of Sandia's microfabricated surface electrode traps to host a chain of trapped Yb-171 ions harnessing their high-fidelity gate operations, indistinguishability, qubit connectivity, and routes to scalability. Here, we present the experimental development of QSCOUT, along with design decisions and hardware details, the capabilities of the testbed, and opportunities for use of this platform. We also discuss some of the first algorithms run on this machine. |
Follow Us |
Engage
Become an APS Member |
My APS
Renew Membership |
Information for |
About APSThe American Physical Society (APS) is a non-profit membership organization working to advance the knowledge of physics. |
© 2024 American Physical Society
| All rights reserved | Terms of Use
| Contact Us
Headquarters
1 Physics Ellipse, College Park, MD 20740-3844
(301) 209-3200
Editorial Office
100 Motor Pkwy, Suite 110, Hauppauge, NY 11788
(631) 591-4000
Office of Public Affairs
529 14th St NW, Suite 1050, Washington, D.C. 20045-2001
(202) 662-8700