Bulletin of the American Physical Society
APS March Meeting 2018
Volume 63, Number 1
Monday–Friday, March 5–9, 2018; Los Angeles, California
Session R33: Superconducting Circuits: Design and PackagingFocus
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Sponsoring Units: DQI Chair: Matteo Mariantoni, University of Waterloo Room: LACC 408B |
Thursday, March 8, 2018 8:00AM - 8:36AM |
R33.00001: Implementations of Superconducting Circuits for Quantum Computing Invited Speaker: David Pappas Quantum circuit materials, fabrication, and measurements have been optimized over the past decade in an intricate feedback loop with system design. This has created what some refer to as the second quantum revolution. While relying on the fundamental building blocks of non-linear aluminum oxide Josephson junctions, the field has been witness to dramatic improvements in coherence every few years. This progress is spurred on as researchers incorporate knowledge from other fields and technologies such as how to identify and mitigate losses due to, e.g. two-level fluctuators in amorphous materials and contamination, to implementing large-scale circuits with multi-chip modules and new quantum limited amplifiers. In this talk we will highlight successes of the various approaches in the field to give context to some of our work at NIST on novel junction fabrication; self-aligned, planarizable lithography for resonators and amplifiers; and new packaging and superconducting film technologies to improve the scalability of the circuits and accessibility of the technology |
Thursday, March 8, 2018 8:36AM - 8:48AM |
R33.00002: Flip Chip Packaging for Superconducting Quantum Computers Adel Elsherbini, Javier Falcon, Jeanette Roberts, Roman Caudillo, Stefano Poletto, Ye Seul Nam, David Michalak, Lester Lampert, Zachary Yoscovits, Joe Saucedo, Alessandro Bruno, James Clarke, Leonardo DiCarlo
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Thursday, March 8, 2018 8:48AM - 9:00AM |
R33.00003: Die Design and Fabrication for Flip-Chip-Packaged Superconducting Quantum Processors Roman Caudillo, Zachary Yoscovits, Lester Lampert, David Michalak, Adel Elsherbini, Javier Falcon, Jeanette Roberts, Leonardo DiCarlo, James Clarke Quantum processors based on superconducting materials with transmon qubits present many scale-up fabrication challenges such as spurious resonances from larger cavity sizes needed to accommodate larger die sizes, tighter tolerances needed for fabrication of a multitude of coplanar waveguide (CPW) resonators coupled to individual feedlines, and excellent process control of Josephson Junction (JJ) fabrication for reliable qubit frequency targeting across large areas. Through silicon vias (TSVs) were developed for improvement of RF hygiene to eliminate spurious resonance modes that can occur due to the larger die sizes. The TSVs are superconducting, which enables the connection of the qubit ground plane to the back plane enabling improved grounding during operation in a dilution refrigerator. Superconducting circuit elements are fabricated from a NbN film chosen for its high kinetic inductance and deposited with a state-of the art tool with excellent cross-wafer uniformity. Aluminum JJs are fabricated using angled-evaporation and cross-wafer uniformity and reliability are studied. Under-bump metallization is studied for optimal assembly to a flip-chip package utilizing Indium-based ball grid array (BGA). The design and fabrication are verified on S17 and S49 quantum chips. |
Thursday, March 8, 2018 9:00AM - 9:12AM |
R33.00004: Towards large-scale superconducting quantum annealers: 2.5D packaging technology and application specific architecture Shiro Kawabata, Kazuhiko Endo, Go Fujii, Mutsuo Hidaka, Masakazu Hioki, Kentaro Imafuku, Kunihiro Inomata, Vasilios Karanikolas, Toshihiro Katashita, Katsuya Kikuchi, Hanpei Koike, Satoshi Kohjiro, Masaaki Maezawa, Kazumasa Makise, Shuichi Nagasawa, Hiroshi Nakagawa, Tadashi Nakagawa, Toshihiro Sekigawa, Masahiro Ukibe, Chiharu Watanabe, Takahiro Yamada, Hirotake Yamamori Quantum annealing is a promising technique which leverages quantum mechanics to solve hard combinatorial optimization problems. D-Wave Systems Inc. is the first company to commercialize superconducting quantum annealer in 2011 and ship a new machine with 2000 qubits in 2017. However, integration of larger number of qubits as well as improvement of qubit coherence are required for practical applications. In this talk we will overview our technological integration scheme for large-scale superconducting quantum annealers in AIST. The scalability is achieved by QUIP (QUbit, Interposer and Package substrate) structure, which is based on our multi-layer fabrication and multi-chip 2.5D packaging technology, e.g., Through Silicon Via (TSV) and flip-chip bonding. We have also developed an Application Specific Annealing Computing (ASAC) architecture in order to increase the available hardware budget and reduces the cost and time for R&D. In addition, we will show our theoretical researches on superconducting quantum annealers. |
Thursday, March 8, 2018 9:12AM - 9:24AM |
R33.00005: Scalable device structure for large-scale superconducting quantum annealing machines Mutsuo Hidaka, Masaaki Maezawa, Kazumasa Makise, Shuichi Nagasawa, Takahiro Yamada, Kunihiro Inomata, Go Fujii, Hirotake Yamamori, Masahiro Ukibe, Shiro Kawabata Practical superconducting quantum annealing machines are expected to have more than one million qubits. However, the number of qubits on a chip is limited to several tens of thousands, because miniaturization of flux-qubits which are the optimum qubit for annealing is restricted by the value of single flux quanta. We propose a multi-chip device structure called QUIP (Qubit-chip/ Interposer/ Package-substrate) in which qubit chips consisting of qubits and couplers are flip-chip connected to active interposers including readout and control circuits and a number of them are placed on a package substrate which has electrical signal lines and I/O pads. Circuits on the active interposer are connected to the signal lines by way of TSVs in the interposers and the adjacent interposers are connected with a bridge interposer. We think this 2.5D structure is the best one for the annealing devices, because QUIP can expand to horizontal direction with keeping same temperature of qubits. We estimated a quantum annealing device consisting of one million qubits was implemented on a 90 mm square package substrate by using the QUIP structure. |
Thursday, March 8, 2018 9:24AM - 9:36AM |
R33.00006: Superconducting solder bumping technology for scalable quantum annealing machines Kazumasa Makise, Masaaki Maezawa, Mutsuo Hidaka, Hiroshi Nakagawa, Katsuya Kikuchi Three-dimensional packaging of superconducting quantum bits is one of the most important technologies for large scale quantum annealing machines. In this work, we are focusing on how to make hundreds of thousands levels of DC connections reliably. Therefore, some properties of the superconducting bumps for flip-chip bonding consisting of a large number of bumps were investigated in details. Superconducting solder bumping test chips were designed for QUIP (Qubit-chip, Interposer and Package-substrate). The test devices consist of a 7.5 mm-square top chip and an 8.5 mm-square base chip. Nb/Ti/Au contact pads for placing were fabricated on Si substrates. To obtain electrical properties of a large number of interconnects, we design and fabricate about 10000 circular lead solder bumps with a 10 um diameter on the top chip and Nb/Ti/Au-opposing-contact pads on the base chip to form a daisy chain of about 10000 chip-to-chip interconnects. We chose lead as the solder material because it has a relatively high critical temperature of 7.2 K and we can check superconducting connection using liquid He and/or conventional refrigerators. |
Thursday, March 8, 2018 9:36AM - 9:48AM |
R33.00007: Fabrication of Sn-filled superconducting through-silicon vias (SC-TSV) for large-scale superconducting quantum circuits Go Fujii, Masahiro Ukibe, Kazumasa Makise, Mutsuo Hidaka, Shuichi Nagasawa, Hirotake Yamamori, Kunihiro Inomata, Takahiro Yamada, Shiro Kawabata
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Thursday, March 8, 2018 9:48AM - 10:00AM |
R33.00008: Enabling technologies for increased circuit complexity of high-coherence superconducting qubits: Part 1 Jonilyn Yoder, David Kim, Peter Baldo, Gregory Calusine, Alexandra Day, George Fitch, Michael Hellstrom, Eric Holihan, David Hover, Bethany Niedzielski, Brenda Osadchy, Danna Rosenberg, Gabriel Samach, Steven Weber, William Oliver Air bridge crossovers are an enabling technology for high-coherence superconducting qubit circuits that provide an additional routing layer to increase circuit complexity. MIT Lincoln Laboratory also has integrated superconducting crossovers into high-coherence superconducting qubits and used them to increase coupling strength between qubits by facilitating coplanar, interwoven qubit loops with large mutual inductances. Here we will describe further development of crossovers with a broad range of simultaneously patterned air bridge lengths and corresponding characterization of the crossovers. |
Thursday, March 8, 2018 10:00AM - 10:12AM |
R33.00009: Enabling technologies for increased circuit complexity of high-coherence superconducting qubits: Part 2 David Kim, Jonilyn Yoder, Rabindra Das, Danna Rosenberg, Peter Baldo, Gregory Calusine, Michael Hellstrom, Bethany Niedzielski, Justin Mallek, Alexander Melville, Brenda Osadchy, Donna-Ruth Yost, Livia Racz, William Oliver As quantum computing with superconducting qubits increases in complexity, 3D integration will enable increased density of control and readout circuitry. One approach is to bond chips that perform different functionalities using indium bumps. MIT Lincoln Laboratory has integrated silicon hard-stop mesas to achieve reliable spacing and tilt between chips during bump bonding. Here we will describe further development of hard-stop mesas, assessment of tilt and integration into high-coherence superconducting qubit fabrication. |
Thursday, March 8, 2018 10:12AM - 10:24AM |
R33.00010: Extending Plane Breaking Pogo Packaging to a Lattice of 17 Superconducting Qubits Nicholas Bronn, Vivekananda Adiga, Salvatore Olivadese, Oblesh Jinka, Xian Wu, Jerry Chow, David Pappas High coherence pogo pin packaging for breaking the plane in a 7-qubit lattice of superconducting qubits in a non-trivial topology was recently demonstrated [1]. Here, we extend this work to a 17-qubit section of the surface code for eventual testing of a distance 3 logical-qubit memory. We report on observed coherences as well as crosstalk between qubits. |
Thursday, March 8, 2018 10:24AM - 10:36AM |
R33.00011: 3D Integration for Superconducting Qubits: Part 1 Danna Rosenberg, Gregory Calusine, Rabindra Das, Alexandra Day, Evan Golden, Amy Greene, Simon Gustavsson, Philip Krantz, David Kim, Morten Kjaergaard, Justin Mallek, Alexander Melville, Bethany Niedzielski, Mollie Schwartz, Steven Weber, Wayne Woods, Jonilyn Yoder, Donna-Ruth Yost, Andrew Kerman, William Oliver As the field of superconducting quantum computing advances from the few-qubit scale, it will become increasingly important to develop techniques for addressing large number of qubits without degrading their performance. 3D integration can alleviate interconnect crowding and enable the construction of large-scale arrays of coupled coherent superconducting qubits. I will present our recent work on developing and characterizing 3D integration components for quantum annealing, including indium bumps and superconducting through-silicon vias, and discuss progress towards building 3D integrated coupled qubits. |
Thursday, March 8, 2018 10:36AM - 10:48AM |
R33.00012: 3D Integration for Superconducting Qubits; Part 2 Superconducting Through Silicon Via Interposer Fabrication Donna-Ruth Yost, Justin Mallek, Danna Rosenberg, Greg Calusine, Matthew Cook, Rabindra Das, Alexandra Day, Evan Golden, David Kim, Alexander Melville, Corey Stull, Wayne Woods, Jonilyn Yoder, Andrew Kerman, William Oliver Quantum annealing requires addressing and connecting an array of qubits. Integration requirements are driven by performance requirements, including high connectivity, low dissipation, and high qubit coherence. In this talk we describe our process flow for fabricating wafers with superconducting through silicon vias (TSVs) leveraging commercial 3D integration tools and techniques. This work demonstrates a means to control and readout an array of superconducting qubits. |
Thursday, March 8, 2018 10:48AM - 11:00AM |
R33.00013: Superconducting Through Silicon Vias (TSVs) for 3D Integration in Quantum Computing Justin Mallek, Donna-Ruth Yost, Danna Rosenberg, Greg Calusine, Matthew Cook, Rabindra Das, Evan Golden, David Kim, Alexander Melville, Corey Stull, Wayne Woods, Jonilyn Yoder, William Oliver Three dimensional integration is an enabling technology for quantum computing. As we progress toward many-qubit systems which require rapidly increasing circuit connectivity one approach is to route qubit control and readout through an interposer layer containing superconducting TSVs. We report on the fabrication of high aspect ratio (>10:1) superconducting TSVs and discuss electrical and reliability data on single vias and long via chains. |
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