Bulletin of the American Physical Society
APS March Meeting 2010
Volume 55, Number 2
Monday–Friday, March 15–19, 2010; Portland, Oregon
Session Y21: Focus Session: Graphene: Field-Effect Devices |
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Sponsoring Units: DMP Chair: Marc Bochrath, University of California, Riverside Room: Portland Ballroom 251 |
Friday, March 19, 2010 8:00AM - 8:12AM |
Y21.00001: FET device with suspended graphene Jian Ming Lu, Zi Kang Tang Because of its linear electronic dispersion, graphene has been intensively studied for electronic application. Top-gated FET device has been measured [1]. Here we study the FET with high quality suspended graphene under high source-drain bias voltage. In addition, two-dimensional temperature distribution of the whole device has been detected by the Raman shift of its 2D peak around 2700cm$^{-1}$. \\[4pt] [1] Inanc Meric et al. \textit{Nature Nanotechnology} \textbf{3}, 654 - 659 (2008). [Preview Abstract] |
Friday, March 19, 2010 8:12AM - 8:24AM |
Y21.00002: Graphene field-effect transistors built with graphene-oxide gate dielectric Brian Standley, Anthony Mendez, Emma Schmidgall, Marc Bockrath Graphene's high mobility and two dimensional nature make it an attractive material for field-effect transistors. Previous efforts in this area have used bulk materials for the gate dielectric, such as SiO$_2$ or HfO$_2$. In contrast, we are investigating the use of an ultra-thin layered material - graphene's insulating analog, graphene oxide. To this end, we have fabricated transistors composed of single or bilayer graphene channels, few-layer graphene oxide gate insulators, and metal top gates. The gates show relatively minimal leakage: less than 0.1 nS/$\mu m^2$ at 300K for a few nanometer thick insulator layer, improving with decreasing temperature. We will present our efforts to characterize these devices, including an estimation of graphene oxide's dielectric constant. [Preview Abstract] |
Friday, March 19, 2010 8:24AM - 8:36AM |
Y21.00003: High mobility monolayer graphene over a 150mm substrate Jinseong Heo, Yun Sung Woo, David H. Seo, Hyun-Jong Chung, Sunae Seo We report the fabrication of monolayer graphene field effect devices over a 150 mm substrate. Using Cu-Ni multilayer growth substrates with Inductively Coupled Plasma-Enhanced Chemical Vapor Deposition (ICPCVD) at 700?, we were able to obtain unprecedented uniformity of monolayer graphene over the entire substrate, confirmed with Raman spectroscopic mapping after metal etching and transfer process. Mobility up to 9,000 cm2V-1s-1 was measured at room temperature by 4-probe technique and temperature dependent characteristics of sample resistivity will also be discussed. [Preview Abstract] |
Friday, March 19, 2010 8:36AM - 9:12AM |
Y21.00004: Charge transport in graphene field effect transistors with ferroelectric gating Invited Speaker: Recent experiments on ferroelectrically gated graphene field effect transistors (GFeFETs) open new opportunities for exploring new graphene physics and functionalities. The non-linear, hysteretic dielectric response of ferroelectrics introduces non-volatility in GFeFETs, which can be utilized for memory and data storage applications. Here, we present a comprehensive way in understanding and controlling ferroelectric gating in GFeFETs. We quantitatively characterize the hysteretic ferroelectric gating using the reference of an independent background doping (n$_{back})$ provided by normal dielectric gating. More importantly, we prove that n$_{back}$ can be used to control the ferroelectric gating by uni-directionally shifting the hysteretic ferroelectric doping in graphene. Utilizing this electrostatic effect, we demonstrate symmetrical bit writing in graphene-ferroelectric FETs with resistance change over 500{\%} and reproducible no-volatile switching over 10$^{5}$ cycles. In the quantum hall regime (2K and 9T), by controlling the polarization magnitude in the ferroelectric dielectric layer, we observe additional integer quantization steps besides the well-known (N+1/2)e$^{2}$/h steps. We also explore the possibility to introduce ultra-high charge carrier doping in graphene by ferroelectric gating. [Preview Abstract] |
Friday, March 19, 2010 9:12AM - 9:24AM |
Y21.00005: Novel Graphene Devices by Precision Transfer Method Cory Dean, Inanc Meric, Andrea Young, Changgu Lee, Natalia Baklitskaya, Philip Kim, Jim Hone, Ken Shepard Hexagonal BN (h-BN) represents the insulator analogue of graphene, sharing identical crystal structure but with B and N atoms each comprising the two sublattices. Owing to its large bandgap, chemical inertness, hexagonal lattice structure (with only 2{\%} lattice mismatch to graphene), planar (i.e. atomically flat) surface structure and good dielectric properties, single crystall h-BN represents a promising alternative to SiO2 as the supporting substrate in graphene FET devices. We discuss our investigation of graphene-BN hybrid devices, realized by precision transfer of mechanically exfoliated graphene and single crystal h-BN flakes. We compare device perfromance of graphene-over-BN with the more conventional graphene-over-SiO2 geometry, and also examine BN as an ultra-thin, crystalline, top-gate dielectric. [Preview Abstract] |
Friday, March 19, 2010 9:24AM - 9:36AM |
Y21.00006: Capacitance of graphenes Andrea Young, Cory Dean, Inanc Meric, Jim Hone, Ken Shepard, Philip Kim Using a transfer procedure and single crystal hexagonal Boron Nitride gate dielectric, we are able to fabricate high mobility graphene devices with local top and back gates. The novel geometry of these devices allows us to measure the spatially averaged compressibility of mono- and bilayer graphene using the ``penetration field'' technique [Eisenstein, J.P. et al. Phys. Rev. Lett. 68, 674 (1992)]. In particular, we analyze the the effects of strong transverse electric fields on the compressibility of graphenes, especially as pertains to charged impurity scattering in single layer graphene and the opening of an energy gap in bilayer. [Preview Abstract] |
Friday, March 19, 2010 9:36AM - 9:48AM |
Y21.00007: Temperature-Dependent Subthreshold Characteristics in Graphene Nanoribbon Tunneling Transistors Youngki Yoon, Sayeef Salahuddin Recently there has been significant interest in band-to-band tunneling field-effect transistors (TFETs) as a means of reducing supply voltage and power dissipation. It is often assumed that the tunneling current should be independent of temperature. By performing an atomistic, self-consistent, quantum transport simulation, we show, to the contrary, that the ballistic tunneling current in a Graphene Nanoribbon (GNR) tunneling transistor should exhibit unique non-linear temperature dependence. Our results show that, in stark contrast to a conventional FET where the subthreshold swing (S) increases linearly with temperature (T), the swing vs. temperature in a GNR TFET is highly non-linear and shows a negative slope below a certain drain current. This negative slope is in good agreement qualitatively with a previous experimental observation in a carbon nanotube TFET, which is a very closely related material system. A method to characterize the distinguishing non-linearity with temperature and drain current is also proposed. [Preview Abstract] |
Friday, March 19, 2010 9:48AM - 10:00AM |
Y21.00008: Effect of SiO$_{2}$ surface treatment on graphene transistors fabricated on Si:SiO$_{2}$ substrates using a lithography free process Prasoon Joshi, Vijay Toutam, Srinivas Tadigadapa, Adam Neal, Humberto Gutierrez Reversal of p-doping to n-doping and hysteresis effects in graphene transistors on Si:SiO$_{2}$ have been reported before. In this detailed experimental study, comparison is made between electronic transport characteristics of single graphene layer transistors where the SiO$_{2}$ is subjected to different surface treatments such as, exposure to O$_{2}$ plasma (1), passivation with hexamethlydisilazane (2) and baking at 300 \r{ }C (3) in laboratory ambient prior to graphene exfoliation. Time constants for the reversal of p-doping in vacuum at 298K are found to be smaller for surface treatments (2) and (3) in comparison to (1). Hysteresis effects are also suppressed in graphene transistors made with surface treatments (2) and (3) . The hysteresis in samples made with surface treatment (1) can be reduced by vacuum annealing as has been suggested before. However, all lithography free samples show reduced hysteresis compared to already published results even in as-fabricated condition. [Preview Abstract] |
Friday, March 19, 2010 10:00AM - 10:12AM |
Y21.00009: Graphite based Schottky diodes formed semiconducting substrates Todd Schumann, Sefaattin Tongay, Arthur Hebard We demonstrate the formation of semimetal graphite/semiconductor Schottky barriers where the semiconductor is either silicon (Si), gallium arsenide (GaAs) or 4H-silicon carbide (4H-SiC). The fabrication can be as easy as allowing a dab of graphite paint to air dry on any one of the investigated semiconductors. Near room temperature, the forward-bias diode characteristics are well described by thermionic emission, and the extracted barrier heights, which are confirmed by capacitance voltage measurements, roughly follow the Schottky-Mott relation. Since the outermost layer of the graphite electrode is a single graphene sheet, we expect that graphene/semiconductor barriers will manifest similar behavior. [Preview Abstract] |
Friday, March 19, 2010 10:12AM - 10:24AM |
Y21.00010: Local Ambipolar Graphene Field Effect Transistors via Metal Side Gates Jifa Tian, Luis Jauregui, Gabriel Lopez, Helin Cao, Yong Chen We fabricated local graphene field effect transistors (FET) based on metal side gates. The characteristic ambipolar field effect of graphene device was observed by sweeping only the voltage of a local metal side gate. The local charge neutrality point of the side-gate graphene FET can be tuned in a large voltage range from positive to negative by a second side gate. Furthermore, we observed that the field effect due to the side gate can be appreciably weakened by electrically grounding the back gate compared to floating the back gate. The experimental results can be well explained by electrostatic simulation using COMSOL. Our technique offers a simple method for local tuning of charge density of graphene nanodevices while avoiding coating graphene surface with dielectrics, which may cause contamination and degradation of graphene. [Preview Abstract] |
Friday, March 19, 2010 10:24AM - 10:36AM |
Y21.00011: Optimization of Graphene Field-Effect Transistors for RF Applications Hsin-Ying Chiu, Yu-Ming Lin, Keith A. Jenkins, Damon B. Farmer, Alberto Valdes-Garcia, Phaedon Avouris Graphene has been demonstrated as a promising material for high frequency field-effect transistors (FETs). Here we present dc and high-frequency characterization of dual-gated graphene FETs where the performance is improved by reducing the access resistance using electrostatic doping via back gate. With a carrier mobility of 2500 cm$^{2}$/Vs, we demonstrate a cut-off frequency of 50 GHz in a 350-nm gate length device, which exceeds that of Si MOSFETs with the same gate length, illustrating graphene's potential for RF applications. Related issues in optimization of graphene FETs will also be discussed, including device geometry, parasitic impedance, metal contact, gate length dependence and dielectrics selections. Ref. Y.-M. Lin \textit{et al}, \textit{IEEE} \textit{Electron Device Letters} (in press) [Preview Abstract] |
Friday, March 19, 2010 10:36AM - 10:48AM |
Y21.00012: Heteroepitaxial Graphene on a Si Substrate Field-Effect Transistor Roman Olac-vaw, Hyun Chul Kang, Tsuneyoshi Komori, Tatayuki Watanabe, Hiromi Karasawa, Yu Miyamoto, Hiroyuki Handa, Hirokazu Fukidome, Tetsuya Suemitsu, Maki Suemitsu, Vladimir Mitin, Taiichi Otsuji Electronic and optoelectronic properties of the graphene-backgate transistor are presented. Our transistor was fabricated on graphene film heteroepitaxially formed by the thermal decomposition on the surface of 3C-SiC grown on a Si substrate by organo-silane gas source molecular beam epitaxy. The film consists of a few graphene layers. Although some gate leakage current is observed, the experimental results show that our device works as an n-type transistor as well as an infrared photovoltaic transistor. The graphene channel saturated current is on the order of mA/mm. The estimated effective mobility has its maximum over 6000 cm$^{2}$/(Vs). The photo-responsivity can be achieved up to mA/W. The backgate voltage tuning spectral characteristic is also observed. Heteroepitaxial graphene is a promising material for post-Si CMOS applications. [Preview Abstract] |
Friday, March 19, 2010 10:48AM - 11:00AM |
Y21.00013: Scanning Tunneling Microscopic Studies of Dielectric Gate Materials on Graphene M.L. Teague, T.-P. Wu, M.W. Bockrath, N.-C. Yeh, C.N. Lau We report on scanning tunneling microscopic and spectroscopic studies of single/bi-layer graphene sheets in contact with dielectric gate materials such as SiO$_{2}$, Al$_{2}$O$_{3}$ and nitric oxide. Previous studies have shown direct correlation between the tunneling conductance and the SiO$_{2}$ substrate-induced strain field. Theoretical analysis based on a scenario of inelastic out-of-plane phonon-assisted tunneling reveals that phonon frequency increases with increasing strain from 26 meV in relaxed regions to 42 meV in strained regions, and a sudden increase at 0.5{\%} strain may be due to a threshold coupling of the out-of-plane graphene phonon with the phonons of the underlying SiO$_{2}$ These findings suggest strong influences of the dielectric materials that came in contact with graphene. Further comparison among different dielectrics will be made to elucidate the underlying causes for these effects. Additionally, spectroscopic studies of the quality of large scale copper-mesh grown graphene will be reported. This work was supported by NSF/NRI under Caltech/CSEM. [Preview Abstract] |
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