Bulletin of the American Physical Society
2009 APS March Meeting
Volume 54, Number 1
Monday–Friday, March 16–20, 2009; Pittsburgh, Pennsylvania
Session B5: Heterogeneous Integration on Silicon |
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Sponsoring Units: FIAP Chair: Ganesh Samudra, National University of Singapore Room: 401/402 |
Monday, March 16, 2009 11:15AM - 11:51AM |
B5.00001: Scaling Properties of High Performance Ge-Si$_x$Ge$_{1-x}$ Core-Shell Nanowire Field Effect Transistors Invited Speaker: Semiconductor nanowires (NWs), namely highly anisotropic crystals with diameters of the order of a few tens of nanometers, have received increased interest recently as a platform for electronics devices, motivated in part by issues associated with end of the roadmap of complementary metal-oxide-semiconductor (CMOS) device scaling. The performance advantage of such devices stems from superior electrostatic properties compared to planar devices, which in turn help increase their on-state current and on/off-state current ratio. We present recent results on the growth and fabrication of a few key NW device structures, which can potentially outperform conventional CMOS devices. By combing axial Ge NW growth, via the vapor-liquid-solid mechanism, with conformal Si$_x$Ge$_{1-x}$ growth by ultra-high-vacuum chemical vapor deposition, we demonstrate Ge-SixGe1-x core-shell NW heterostructures. Transmission electron microscopy combined with energy dispersive X-ray spectroscopy show that the Si$_x$Ge$_{1-x}$ shell can be grown in-situ, epitaxial onto the Ge NW core, and that the Si/Ge shell content can be tuned depending on the growth conditions, effectively enabling band engineering in these one dimensional nanowire heterostructures. A key component in fabrication high performance nanowire field effect transistors, namely high on-state current and high on/off-state current ratio, is the fabrication of low resistance, unipolar contacts to a semiconductor nanowire. Using low energy ion implantation we demonstrate dual-gated Ge-Si$_x$Ge$_{1-x}$ core-shell nanowire field effect transistors with highly doped source and drain. We discuss the scaling properties as a function of channel length, and intrinsic carrier mobility in these devices. [Preview Abstract] |
Monday, March 16, 2009 11:51AM - 12:27PM |
B5.00002: Integration of CNTs with Silicon Invited Speaker: In this talk, the growth and characterisation of both single and multi wall CNTs is described and a realistic appraisal of the future of CNTs in the electronics field will be provided. Although they are less likely, in the author's opinion, to take over from silicon for use in the active devices such as transistors and diodes etc. in logic circuits their use in vias and interconnects in next generation integrated circuits is considered as being entirely feasible as is their use in transparent conducting contacts. Another major contribution to future electronics could be in complementary applications to CMOS such as their use in sensors, thermal interface materials and solder joints. A novel Liquid Crystal Over Silicon (LCOS) structure will also be discussed. [Preview Abstract] |
Monday, March 16, 2009 12:27PM - 1:03PM |
B5.00003: Heterogeneous Integration of Materials on Si for Nanophotonics Devices Invited Speaker: Optical interconnects are attractive candidates for achieving communication bandwidth well beyond terabit-per-second for high-performance multi-core microprocessors. Silicon has become a desirable material due to its transparency in the infrared wavelength range and the ease for integrating optical devices at the vicinity of CMOS circuitry utilizing standard processes. While state-of-the-art patterning techniques provide precise dimension control as well as pattern placement, standard doping and metallization steps enable utilization of phenomena such as carrier injection and depletion to render the devices tunable. As a result, large progress has been made on Si-based nanophotonic devices such as modulators, switches, and wavelength division multiplexing (WDM) systems [1, 2]. To make photodetectors, however, a heterogeneous integration of other materials that absorb light in the infrared is necessary. Available in standard front-end CMOS processes for gate strain engineering, Germanium is suitable due to its high absorption coefficient at 1.3$\mu $m and 1.5$\mu $m wavelengths. Thus, Ge can be directly integrated into the process to fabricate compact photodetectors simultaneously with amplifier circuits in order to make a receiver for an optical network. Nevertheless, the integration of Ge photodetector into the CMOS process flow is very challenging due to process complexity and severe temperature constraints; as a result, photodetectors fabricated only after completing the front-end processes have been previously demonstrated. This talk will discuss Ge waveguide photodetectors that have been integrated into the front-end before the activation of CMOS well implants. By utilizing a lateral seeded crystallization method wherein the Ge waveguides are melted during high-temperature dopant activation, 20$\mu $m-long single-crystal Ge-on-insulator waveguides were formed. This approach eliminates the need for selective epitaxial growth of Ge, and avoids high-density misfit dislocations formed due to lattice mismatch when growing Ge on Si substrate. The photodetectors operate at low applied bias voltages (0.5-1V) with bandwidth exceeding 40GHz. \\[4pt] [1] W.M.J. Green et al, ``Ultra-compact, low RF power, 10 Gb/s silicon Mach--Zehnder modulator,'' Opt. Express 15, 17106 (2007).\\[0pt] [2] Y. A. Vlasov et al, ``High-throughput Silicon Nanophotonic wavelength-insensitive switch for On-chip Optical Networks,'' Nature Photonics 2, 242 (2008). [Preview Abstract] |
Monday, March 16, 2009 1:03PM - 1:39PM |
B5.00004: Beyond Moore's Law: Heterogeneous Integration of III-N Semiconductors and Si CMOS Electronics Invited Speaker: Moore's law has been one of the main drivers behind the unprecedented development of semiconductors in the last forty years. However, this economical and technological paradigm that has helped to create modern Si electronics is now jeopardizing its future. Traditional Si scaling is not only becoming unaffordable, but the performance improvement due to scaling is diminishing. Our group is working on an approach different from Moore's law to increase the performance of electronics: the heterogeneous integration of different semiconductor materials on the same wafer. In this paper, we describe our work on the seamless integration of GaN-based devices and Si electronics. While Si electronics has shown unsurpassed levels of scaling and circuit complexity, nitride semiconductors offer excellent optoelectronics and high frequency/power electronic properties. The ability to combine these two material systems in the same chip and in extremely close proximity would allow unprecedented flexibility for advanced applications. Using wafer bonding technology, virtual Si (001) / GaN / Si (001) substrates have been fabricated for the first time. Due to the high thermal stability of GaN, Si CMOS electronics can be processed in this new substrates without affecting the nitride layers underneath the surface. After the Si devices are fabricated, the Si material is removed from the regions where nitride devices are needed. Then, the nitride devices (transistors, LEDs, lasers or sensors) are processed at room temperature and, finally, an interconnection layer forms the final hybrid circuits. Using this new technology several hybrid circuits are currently being developed, including high power differential amplifiers and normally-off power transistors. These advanced circuits are just a few examples of the potential of heterogeneous integration and how the close integration of Si and other materials enables a vast array of new exciting opportunities for electronics. [Preview Abstract] |
Monday, March 16, 2009 1:39PM - 2:15PM |
B5.00005: Integration of Ferroelectrics, Ferromagnets, and Multiferroics with Silicon Invited Speaker: In this talk I will describe the epitaxial integration of ferroelectrics, ferromagnets, and materials that are both at the same time, with silicon. Until recently, ``oxide'' could only mean one thing to anyone working in the semiconductor industry---SiO$_{2}$. But oxides are an exciting class of electronic materials in their own right. Oxides exhibit the full spectrum of electronic, optical, and magnetic behavior including many functionalities not found in conventional semiconductors. Further, such oxides can be combined epitaxially not only with each other, but epitaxially with the workhorse of semiconductor technology, silicon, enabling the unparalleled variety of physical properties of oxides to be exploited in new ways for electronic applications. The specific oxides that my collaborators* and I have integrated epitaxially with silicon include EuO, ZnO, CaTiO$_{3}$, SrTiO$_{3}$, BaTiO$_{3}$, BiFeO$_{3}$, Pb(Zr,Ti)O$_{3}$, and PbMg$_{1/3}$Nb$_{2/3}$O$_{3}$-PbTiO$_{3}$. Highlights from these systems will be presented. * The work reported was performed in collaboration with the groups of Jochen Mannhart (U. Augsburg), Chang-Beom Eom (U. Wisconsin-Madison), Ramamoorthy Ramesh (Berkeley), Jeremy Levy (U. Pittsburgh), David Muller (Cornell), Xiaoqing Pan (U. Michigan), J\"{u}rgen Schubert (J\"{u}lich), Long-Qing Chen (Penn State), Susan Trolier-McKinstry (Penn State), Yves Idzerda (Montana State), Peter B\"{o}ni (TU M\"{u}nchen), Joseph Woicik (NIST), Philip Ryan (Ames), Michael Bedzyk (Northwestern), Yuri Barash (Russian Acad. Sci.), Qing Ma (Intel), and Hao Li (Motorola). [Preview Abstract] |
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