Bulletin of the American Physical Society
2008 APS March Meeting
Volume 53, Number 2
Monday–Friday, March 10–14, 2008; New Orleans, Louisiana
Session S2: Can Power Dissipation in a Switch Be Significantly Lowered? |
Hide Abstracts |
Sponsoring Units: FIAP Chair: Jeff Welser, SRC Nanoelectronics Research Initiative Room: Morial Convention Center LaLouisiane C |
Wednesday, March 12, 2008 2:30PM - 3:06PM |
S2.00001: Will a New Milli-Volt Switch Replace the Transistor for Digital Applications? Invited Speaker: In contemplating the headlong rush toward miniaturization represented by Moore’s Law, it is tempting to think only of the progression toward molecular sized components. There is a second aspect of Moore’s Law, that is sometimes overlooked. Because of miniaturization, the energy efficiency of information processing steadily improves. We anticipate that the energy required to process a single bit of information will eventually become as tiny as 1 electron Volt per function, truly indeed a molecular sized energy. Inevitably most logic functions including storage, readout, and other logical manipulations will eventually be that efficient. However there is one information-processing-function that bucks this trend. That is communication, especially over short distances. Our best projections of improvements in the short distance communication function show that it will still require hundreds of thousand of electron Volts, just to move one bit of information the tiny distance of only 10 micro meters. Why this energy per bit discrepancy for communications? It is caused by the difference in voltage scale between the wires and the transistor switches. Transistors are thermally activated, leading to a characteristic voltage >>kT/q. Wires are long and they have a low impedance, allowing them to operate efficiently even at 1milli-Volt. The challenge then is to replace transistors with a new low-voltage switch , that is better matched to the wires. I will present some of the technical options for such a new switch. [Preview Abstract] |
Wednesday, March 12, 2008 3:06PM - 3:42PM |
S2.00002: Use of negative capacitance to provide voltage amplification for ultra low power nanoscale devices Invited Speaker: It is well known that conventional Field Effect Transistors (FET's) require a change in the channel potential of at least 60 mV at 300K to effect a change in the current by a factor of ten, and this minimum subthreshold slope S puts a \textit{fundamental lower limit} on the operating voltage and hence the power dissipation in standard FET based switches. Here we show that by replacing the standard insulator with a ferroelectric insulator of the right thickness it should be possible to implement a \textbf{\textit{step-up voltage transformer}} that will amplify the gate voltage thus leading to values of S lower than 60 mV/decade and enabling low voltage/low power operation. The voltage transformer action can be understood intuitively as the result of an effective negative capacitance provided by the ferroelectric capacitor which arises from an internal positive feedback that in principle could be obtained from other microscopic mechanisms as well. Unlike other proposals to reduce S this involves no change in the basic physics of the FET and thus does not affect its current drive or impose other restrictions. [Preview Abstract] |
Wednesday, March 12, 2008 3:42PM - 4:18PM |
S2.00003: Nanowire Impact Ionization FETs Invited Speaker: One limiting factor in the scaling of transistor technology is the room temperature limit of 60 mV/decade of the inverse sub-threshold slope. As supply- and threshold voltages are scaled down leakage currents rise exponentially causing the standby power of highly integrated circuits to suffer. New types of devices based on band-to-band tunneling [1] or impact ionization [2] have recently been demonstrated that can circumvent the 60 mV/decade limit thereby offering lower leakage currents. We have demonstrated vertical integration [3] of a single surround-gated silicon nanowire field-effect transistor (NW FET) having an inverse sub-threshold slope as low as 6 mV/decade at room temperature that spans four orders of magnitude in current [4]. The transistor shows slopes below 60 mV/decade for supply voltages above 2 V. Due to the use of a top Schottky contact and two ungated regions the devices show ambipolar characteristics with impact ionization for both electron and hole branch. The rather small voltages reduce hot carrier injection into the gate dielectric making threshold voltage shifts and degradation of the performance minimal. \newline [1] J. Appenzeller, et al., Phys. Rev. Lett. \textbf{93}, 196805 (2004). \newline [2] K. Gopalakrishnan, et al., IEDM Tech. Dig., 289 (2002). \newline [3] V. Schmidt et al., Small \textbf{2}, 85 (2006). \newline [4] M. T. Bj\"{o}rk \textit{et al.}, Appl. Phys. Lett. \textbf{90}, 142110 (2007). [Preview Abstract] |
Wednesday, March 12, 2008 4:18PM - 4:54PM |
S2.00004: Nanoelectromechanical switches Invited Speaker: Power dissipation is perhaps the most important problem confronting the electronics industry. To address this issue, we investigate vertical nanoelectromechanical (NEM) switches suitable for complementary logic, reconfigurable interconnects, and static power management. NEM switches have the following advantages: (i) Near elimination of source-drain static tunneling losses, (ii) Improved subthreshold characteristics [1]-- allowing lower operating voltage and hence lower dynamic power dissipation, (iii) Ability to run at much higher temperatures than Si-based CMOS. Our approach employs a carbon nanotube-based relay. We have prototyped this approach by inserting a tube into an etched gap between two contacts. Using a nanopositioner to align the tube, the prototype has demonstrated multiple switching at 5V. We will characterize this device and also integrated NEM switches. \newline [1] Ghosh, A. W., Rakshit, T. \& Datta, S. Gating of a molecular transistor: Electrostatic and Conformational. Nano Letters 4, 565-568 (2004). [Preview Abstract] |
Wednesday, March 12, 2008 4:54PM - 5:30PM |
S2.00005: One-dimensional semiconductors for low-power electronic applications Invited Speaker: Power dissipation is rapidly increasing from one to the next generation of silicon CMOS based chips. While following the ideal scaling rules should improve the performance without significantly increasing the power consumption, in particular the supply voltage has not been reduced in the past as required. Since the gate oxide thickness (SiO(N) in common CMOS applications) on the other hand has been decreased substantially, gate leakage currents have become a severe problem when the transistor is turned off. For logic applications, part of the applied voltage is used to switch the device from its off-state into its on-state while the other portion is used to drive the transistor into a regime of high transconductance. When asking the question about how to decrease the supply voltage to reduce power consumption of the device, both states have to be taken into account. Considering that currently more than 3 orders of magnitude current change are required to ensure proper circuit operation, already around 200mV of the supply voltage are used towards driving the transistor from the off-state to the on-state. This is true for charge-based devices that control current transport by means of a gate dependent barrier that can only be overcome by thermal emission. Those types of devices are characterized by an inverse subthreshold slope larger than around 60mV/dec. Altering the logic state by applying smaller voltages is highly desirable. My presentation will elucidate on the possibility of using band- to-band tunneling in carbon nanotubes as a viable approach to address both of the above aspects -- the transistor off- and on- state performance. I will use the example of carbon nanotube based devices to discuss various switching concepts in these low-dimensional geometries and to argue why a certain device structure should be favored over another. [Preview Abstract] |
Follow Us |
Engage
Become an APS Member |
My APS
Renew Membership |
Information for |
About APSThe American Physical Society (APS) is a non-profit membership organization working to advance the knowledge of physics. |
© 2024 American Physical Society
| All rights reserved | Terms of Use
| Contact Us
Headquarters
1 Physics Ellipse, College Park, MD 20740-3844
(301) 209-3200
Editorial Office
100 Motor Pkwy, Suite 110, Hauppauge, NY 11788
(631) 591-4000
Office of Public Affairs
529 14th St NW, Suite 1050, Washington, D.C. 20045-2001
(202) 662-8700