Bulletin of the American Physical Society
2008 APS March Meeting
Volume 53, Number 2
Monday–Friday, March 10–14, 2008; New Orleans, Louisiana
Session Q35: Focus Session: Emerging Materials and Devices III |
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Sponsoring Units: FIAP DMP Chair: Jeff Welser, IBM Almaden Room: Morial Convention Center 227 |
Wednesday, March 12, 2008 11:15AM - 11:51AM |
Q35.00001: Advanced SOI CMOS transistor technology for high performance microprocessors Invited Speaker: An overview of state of the art Silicon on Insulator CMOS transistors used for 65nm and 45nm volume manufacturing of microprocessors will be given. AMD's unique technology and transistor progression model as well as the key challenges to increase the power efficiency of microprocessor products will be described. For advanced SOI transistors stress engineering has become a standard feature since the 90nm technology node due to gate oxide scaling limitations [1]. Especially techniques which induce local strain such as compressive and tensile stressed over-layer films, embedded-SiGe, and stress memorization, are keys to enhance transistor and product performance. With optimization, the different stressors are highly compatible and additive to each other, improving PMOS and NMOS saturation drive currents by ca. 50{\%} and 30{\%}, respectively [2]. In addition to reducing the lateral and vertical device dimensions advanced (Laser or Flash) annealing has been applied [3]. These anneal processes yield an improved dopant activation for active and gate regions resulting in lower source-drain resistance and gate depletion without any additional diffusion. To achieve a ``high performance per watt'', technology and design optimization is required. Technology elements like SOI, stressors, multiple gate oxides needed hand-in-hand development with multiple core designs and power efficient microprocessor architectures. These techniques have been applied and optimized for 65nm and 45nm manufacturing. Future technology options, like strained silicon directly bonded on SOI, Si:C embedded SD and High K gate oxide will be discussed. \newline [1] M. Horstmann, et al., IEDM 2005, p. 243 \newline [2] A. Wei et al., VLSI 2007 \newline [3] Th.Feudel et al., RTP Conference, Kyoto, 2006 [Preview Abstract] |
Wednesday, March 12, 2008 11:51AM - 12:03PM |
Q35.00002: Elastically strained silicon/silicon dioxide nano-layers Leonid Tsybeskov, Andrei Sirenko, David Lockwood, John McCaffrey Traditional fabrication of strained Si nanostructures (nano-layers, nano-tubes, nano-belts and nano-membranes) involves lattice mismatched Si/SiGe heteroepitaxy. In this paper, we demonstrate that elastically-strained, high aspect ratio Si nano-layers can be fabricated using a modified procedure of a-Si/SiO2 deposition followed by thermal annealing. We find that the mismatch between Si and SiO2 thermal expansion coefficients prevents the thermal crystallization of amorphous Si near Si/SiO2 interfaces and that this phenomenon can be used to direct crystallization of nanometer-thick Si layers. These more than micron in lateral dimension Si nano-layers with thickness of $\sim $ 10 nm exhibit a very low density of structural defects and remain elastically strained with respect to the Si substrate. [Preview Abstract] |
Wednesday, March 12, 2008 12:03PM - 12:15PM |
Q35.00003: Electronic Structure of Conduction Bands in Strained Si Nanomembranes C. Euaruksakul, Z. Li, C.S. Ritz, B. Tanto, D.M. Cottrill, M.-H. Huang, F. Chen, D.E. Savage, F. Liu, F.J. Himpsel, M.G. Lagally We observe energy shifts of several conduction bands and a splitting of the conduction band minimum in elastically strained Si(001) and Si(110) Si nanomembranes (NMs) using X-ray absorption spectroscopy from the Si 2p core level. The surface sensitivity of absorption spectroscopy with electron yield detection makes the method suitable for studying very thin strained layers. Elastically strained NMs are dislocation free and thus provide an excellent model for determining the relationship of energy levels and strain. We measure the change in the global conduction band minima near the six X-points and also higher minima at the L and $\Gamma $ points, which yield information about the direction of the absolute energy shift due to the strain. Quantitative values of the level positions, including the core levels, are provided and compared to theory. [Preview Abstract] |
Wednesday, March 12, 2008 12:15PM - 12:27PM |
Q35.00004: Inelastic Electron Tunneling Spectroscopy Study of MOS Diodes Based on High-$\kappa $ Gate Dielectrics S.L. You, C.C. Huang, C.J. Wang, H.C. Ho, J. Kwo, W.C. Lee, K.Y. Lee, Y.D. Wu, Y.J. Lee, M. Hong Inelastic electron tunneling spectroscopy was applied to characterize the microstructure, interface, and trap-related states in silicon MOS diodes made of high $\kappa $ gate dielectrics HfO$_{2}$, Y$_{2}$O$_{3}$, and stacked HfO$_{2}$/Y$_{2}$O$_{3}$ bilayers by molecular beam epitaxy and atomic layer deposition under various heat treatments. Reproducible vibrational modes of monoclinic HfO$_{2 }$and cubic Y$_{2}$O$_{3}$ were identified from IETS spectra. The gate bias dependence of the spectrum enables to ascribe the phonon modes adjacent to the lower or upper interface. A simple modeling was employed to analyze the trap related features in the spectra of stacked HfO$_{2}$/Y$_{2}$O$_{3}$ bilayers, and showed that most traps are located near the HfO$_{2}$/Y$_{2}$O$_{3}$ interface due to dissimilar charge distributions of two ionic oxides of different cation valences, and the interfacial strains of dissimilar structures. Work is now extended to Y-doped HfO$_{2}$ films in cubic phase with an enhanced $\kappa $ over 30. [Preview Abstract] |
Wednesday, March 12, 2008 12:27PM - 12:39PM |
Q35.00005: On the role of Al doping at the SiO$_{2}$/HfO$_{2}$ interface Onise Sharia, A.A. Demkov, G. Bersuker, B.H. Lee One of the main challenges associated with the integration of high-k gate dielectrics such as hafnia is the identification of metal electrodes exhibiting the work function aligned with Si band edges. Due to the inherent instability of metals in contact with hafnia under high temperature, the focus has recently shifted towards developing a metal gate stack with appropriate effective work functions (EWF), which would result in the required low transistor threshold voltage. In this talk we report the theoretical results on doping the SiO$_{2}$/HfO$_{2}$ gate stack with Al atoms which, as we show, controls the EWF. We consider several dopant-vacancy models in various positions with respect to the interface. The proper stoichiometry avoiding fixed charge is maintained in all models. We find that doping at the interface has lower energy than doping in the bulk of silica or hafnia, which suggests the segregation of Al atoms towards the interface. Importantly, in all cases Al-vacancy complexes at the interface significantly change the band alignment, reducing the valence band offset. Thus, doping the SiO$_{2}$/HfO$_{2}$ gate stack with Al atoms offers a consistent way to adjust the alignment. This increase of the EWF can be explained with our previously introduced model that suggests that an oxygen depleted interface provides less effective screening, which in turn increases the interface dipole. [Preview Abstract] |
Wednesday, March 12, 2008 12:39PM - 12:51PM |
Q35.00006: Oxide charge and band alignments in Pt/epi-Lu$_{2}$O$_{3}$/Si (111) structures studied by Internal Photoemission and C-V measurements W. Cai, J.P. Pelz, C. Adamo, D.G. Schlom A variety of rare-earth/transition metal oxide films (of interest as possible ``high-k'' gate dielectrics for future MOS devices) were found to have similar band gap and band alignments to Si, and ``tailing'' conduction band (CB) states extending $\sim $1 eV below the ``primary'' CB [1]. We used internal photoemission/photoconductivity (Int-PE/PC) and capacitance-voltage (C-V) measurements to study 20 nm-thick epitaxial Lu$_{2}$O$_{3}$ film grown at 700 $^{\circ}$C on Si(111). A $\sim $1.5V difference between the oxide- and Si- flat band voltages (measured by PC and C-V respectively) indicates $\sim $6 $\times $ 10$^{12}$ cm$^{-2}$ fixed positive oxide charge, which was mostly removed by a $\sim $350 $^{\circ}$C post-metallization vacuum anneal. Int-PE measurements indicate the CB measured from the metal-side lines up $\sim $0.4 eV below the ``primary'' CB measured from the Si side, in contrast with our finding on Pt/epi-Sc$_{2}$O$_{3}$/Si (111) [2] that the metal-side CB aligned with the tail-state CB. Also, Ballistic Electron Emission Microscopy of Pt/epi-Lu$_{2}$O$_{3}$/Si (111) found $\sim $0.3 - 0.4 eV higher energy barrier than found by Int-PE, suggesting significant transient charge trapping in this sample. Work supported by NSF Grant No. DMR-0505165. [1] V. V. Afanas'ev\textit{ et al}., Appl. Phys. Lett. \textbf{85}, 5917 (2004); \textbf{88}, 032104 (2006). [2] W. Cai\textit{ et al}., Appl. Phys. Lett. \textbf{91}, 042901 (2007). [Preview Abstract] |
Wednesday, March 12, 2008 12:51PM - 1:03PM |
Q35.00007: Electrical and optical properties of PtSi thin films Hendrik Bentmann, A.A. Demkov, Stefan Zollner, Rich Gregory Metal silicides are used in complementary metal-oxide-semiconductor devices (CMOS) to form contacts between metal interconnects and source, drain, and gate silicon of the transistors. They offer important properties like low resistivity, low contact resistance to Si as well as excellent process compatibility with the standard Si technology. Recently, metal silicides have attracted renewed attention and they are a current research topic in the semiconductor industry. We report a joint theoretical and experimental study of thin Pt silicide films. Employing density functional theory (DFT) methods we have investigated the electronic structure as well as bonding and optical properties of PtSi and Pt$_{2}$Si. Additionally, we have calculated surface energies for various orientations and terminations of PtSi surfaces. Our results suggest that thermodynamics plays an important role in the silicide formation. The complex index of refraction determined by spectroscopic ellipsometry exhibits non-Drude behavior and shows peaks, which were identified with inter-band transitions in the d-manifold of platinum and compared to theory. [Preview Abstract] |
Wednesday, March 12, 2008 1:03PM - 1:15PM |
Q35.00008: \textit{Ab-initio} study of early stages of III-V epitaxy on Si : direct \textit{vs.} buffer deposition on vicinal surfaces A.A. Demkov, Onise Sharia, Hendrik Bentmann III-V materials, such as GaAs or InSb as well as other compound semiconductors with high carrier mobility are considered as potential candidates for a channel material in future CMOS-type devices. The most promising route to incorporate these advanced materials into CMOS is by growing epitaxial thin films on Si, either directly or \textit{via} a buffer layer. Direct deposition suffers from a large lattice mismatch, and domain formation caused by the presence of steps on the Si surface. Perovskite oxides such as SrTiO$_{3}$ (STO) offer a possibility to reduce the lattice mismatch between Si and, e.g. GaAs in a step-wise fashion, however, the steps on the semiconductor surface present a somewhat unusual challenge. On the other hand, the use of vicinal surfaces for the direct deposition of GaAs on Si may eliminate the problem of orthogonal domains. Thus understanding the role of steps during the crystal growth is key to both approaches. In this talk we report a theoretical study of STO epitaxy on the vicinal Si(001) surface. In particular, we find that at the early stages of growth, Sr adatoms segregate to the step edges. We also consider the direct epitaxy of III-V compound semiconductors on high index Si surfaces, specifically, the silicon (112) surface. We consider In adsorption on this surface and identify a stable 7x1 substitutional reconstruction which is fundamentally different from a 6x1 reported for Ga. [Preview Abstract] |
Wednesday, March 12, 2008 1:15PM - 1:27PM |
Q35.00009: Atomic-layer-deposited HfO$_{2}$ on In$_{0.53}$Ga$_{0.47}$As -- passivation and energy-band parameters Y.C. Chang, K.Y. Lee, M.L. Huang, Y.J. Lee, T.D. Lin, M. Hong, J. Kwo High $\kappa $ dielectric HfO$_{2}$ films were deposited by atomic layer deposition on air-exposed In$_{0.53}$Ga$_{0.47}$As/InP (100), and found to exhibit an atomically sharp interface free of arsenic oxides, an important aspect for Fermi level un-pinning. Angular-resolved x-ray photoelectron spectroscopy (XPS) using synchrotron radiation, however, observed the existence of Ga$_{2}$O$_{3}$, In$_{2}$O$_{3}$, and In(OH)$_{3}$ at the interface. The I-V of the MOS diode for an HfO$_{2}$ 7.8 nm thick follows the Fowler-Nordheim tunneling mechanism with a low leakage $\sim $10$^{-8 }$A/cm$^{2}$ at V$_{FB}$+1V, and an interfacial density of states $D_{it}$ of 2x10$^{12 }$cm$^{-2}$eV$^{-1}$. A conduction-band offset of $\sim $ 1.8 eV, and a valence-band offset of $\sim $ 2.9 eV were derived from the transport, and XPS data, respectively. For another HfO$_{2 }$film 4.5nm thick we achieved a CET value as small as 1.0nm, and a leakage of 3.8x10$^{-4 }$A/cm$^{2}$ at V$_{FB}$+1V. The good scalability of ALD grown HfO$_{2}$ film with low leakage makes it very promising for III-V MOSFET applications. [Preview Abstract] |
Wednesday, March 12, 2008 1:27PM - 1:39PM |
Q35.00010: Interfacial-layers-free Ga$_{2}$O$_{3}$(Gd$_{2}$O$_{3})$/Ge MOS Diodes C.H. Lee, T.D. Lin, K.Y. Lee, M.L. Huang, L.T. Tung, M. Hong, J. Kwo High $\kappa $ dielectric Ga$_{2}$O$_{3}$(Gd$_{2}$O$_{3})$ films were deposited directly on Ge by Molecular-Beam-Epitaxy without the employment of GeON interfacial layer. Excellent electrical properties, such as a high $\kappa $ value of 14.5, a low leakage current density of only 3x10$^{-9}$ A/cm$^{2}$ at V$_{fb}$+1V, and well-behaved CV characteristics, were demonstrated, even being subjected to a 500$^{\circ}$C annealing in N$_{2}$ ambient for 5 min. An abrupt Ga$_{2}$O$_{3}$(Gd$_{2}$O$_{3})$/Ge interface without any interfacial layer was revealed by high-resolution transmission electron microscopy as well as \textit{in-situ} x-ray photoelectron spectroscopy (XPS). Detailed XPS studies indicate that the oxide/Ge interface consists of mainly Ge-O-Gd bonding, distinctly different from that of native oxide. Furthermore, the 500$^{o}$C annealing did not change the chemical bonding, implying a great thermodynamic stability of the hetero-structure. The outstanding electrical and thermodynamic properties qualified Ga$_{2}$O$_{3}$(Gd$_{2}$O$_{3})$ as a promising dielectric for Ge and proved the GeON interfacial layer to be unnecessary. [Preview Abstract] |
Wednesday, March 12, 2008 1:39PM - 1:51PM |
Q35.00011: Aspect Ratio Study of Microstructures Formed using an Adaptable Photomask Anna Fox, Adam Fontecchio We present an aspect ratio study of microstructures fabricated using a holographically formed polymer dispersed liquid crystal (H-PDLC) adaptable photomask. Recently it has been shown that H-PDLC films can act as electrically controllable light valves to selectively allow transmission of UV exposure in the lithographic process, making it ideal for application as a reconfigurable photomask. This study focuses on comparing aspect ratios of structures patterned using this adaptable photomask and processed with wet etching and reactive ion etching techniques. Aspect ratio comparisons with structures fabricated using a binary mask and etched using an identical process are presented. Results indicate that features formed using an adaptable H-PDLC mask have comparable aspect ratios to features fabricated using a binary mask. H-PDLC is a polymeric material formed holographically to have periodically spaced stratified layers of cured monomer and liquid crystal droplets. Reflection of a particular band of wavelengths occurs due to the periodicity of the layers and the index mismatch of the randomly aligned liquid crystal droplets. Bias applied to the film electrically aligns the liquid crystal layers eliminating the index mismatch yielding a transparent film. [Preview Abstract] |
Wednesday, March 12, 2008 1:51PM - 2:03PM |
Q35.00012: Characterization of surface and pore morphologies on nanoporous organosilicate films Jeeun Kim, Heeju Lee, Sanghoon Song, Wonsuk Cha, Hyunjung Kim, Gunwoo Park, Sungkyu Min, Taehoon Lee, Heewoo Rhee, Gwangwoo Kim We have fabricated nanoporous organosilicate films with reactive~ porogen trimethoxysilyl - propyl - cyclodextrin(TMSCD). With same amount of porogen loading, the films with reactive porogen. TMSCD have shown higher mechanical strength than those with other non-reactive porogen. We have measured~ the pore morphologies depending on the types of porogens and loading densities along the pore generation processes by the grazing incidence small angle x-ray scattering,~ x-ray reflectivity, and ellipsometry. We measured the porosity of the film as a function of time and the annealing condition. We determined the actual porosity by measuring electron density of the films. In low loading density (10{\%}$\sim $40{\%}) pore size is very small and pore distribution is uniform. In high loading density ($>$50{\%}) the pores start to aggregate. We found that the porosity of the films can be affected easily by moisture. The results will be discussed with the mechanical properties along the optimized conditions for the films with ultra low dielectric constant. [Preview Abstract] |
Wednesday, March 12, 2008 2:03PM - 2:15PM |
Q35.00013: Trap densities in porous low-k dielectric thin films as determined by optical and electrical measurements Joanna Atkin, Daohua Song, Robert Laibowitz, Eduard Cartier, Thomas Shaw, Tony Heinz Low-k dielectric materials based on porous carbon-doped oxides (p-CDOs), with relative dielectric constants as low as k = 2.1, are of great interest in the microelectronics industry. Knowledge of their basic electronic properties, such as energy gaps, barrier heights, and trap states, is essential for developing an understanding of their electrical leakage and stability characteristics. In particular, conduction via trap states is known to be an important mechanism for charge transport. We present measurements of the density of trap states in low-k p-CDO films deposited on silicon. The techniques used include photoinduced current transients, optical second-harmonic generation measurements, and C-V electrical characterization. The low-k materials are shown to have relatively high trap densities (as compared with silicon dioxide films). The different behavior of bulk and interface traps will be discussed, along with the effects of annealing in various ambients. [Preview Abstract] |
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