Bulletin of the American Physical Society
2007 APS March Meeting
Volume 52, Number 1
Monday–Friday, March 5–9, 2007; Denver, Colorado
Session N39: Focus Session: Emerging Research Devices and Materials for the Microelectronics Industry I |
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Sponsoring Units: FIAP Chair: Jean Heremans, Virginia Polytechnic Institute and State University Room: Colorado Convention Center 502 |
Wednesday, March 7, 2007 8:00AM - 8:36AM |
N39.00001: Silicide Nanowires for Low-Resistance CMOS Transistor Contacts. Invited Speaker: Transition metal (TM) silicide nanowires are used as contacts for modern CMOS transistors. (Our smallest wires are $\sim$20 nm thick and $\sim$50 nm wide.) While much research on thick TM silicides was conducted long ago, materials perform differently at the nanoscale. For example, the usual phase transformation sequences (e.g., Ni, Ni2Si, NiSi, NiSi2) for the reaction of thick metal films on Si no longer apply to nanostructures, because the surface and interface energies compete with the bulk energy of a given crystal structure. Therefore, a NiSi film will agglomerate into hemispherical droplets of NiSi by annealing before it reaches the lowest-energy (NiSi2) crystalline structure. These dynamics can be tuned by addition of impurities (such as Pt in Ni). The Si surface preparation is also a more important factor for nanowires than for silicidation of thick TM films. Ni nanowires formed on Si surfaces that were cleaned and amorphized by sputtering with Ar ions have a tendency to form NiSi2 pyramids (``spikes'') even at moderate temperatures ($\sim$400$^{\circ}$C), while similar Ni films formed on atomically clean or hydrogen-terminated Si form uniform NiSi nanowires. Another issue affecting TM silicides is the barrier height between the silicide contact and the silicon transistor. For most TM silicides, the Fermi level of the silicide is aligned with the center of the Si band gap. Therefore, silicide contacts experience Schottky barrier heights of around 0.5 eV for both n-type and p-type Si. The resulting contact resistance becomes a significant term for the overall resistance of modern CMOS transistors. Lowering this contact resistance is an important goal in CMOS research. New materials are under investigation (for example PtSi, which has a barrier height of only 0.3 eV to p-type Si). This talk will describe recent results, with special emphasis on characterization techniques and electrical testing useful for the development of silicide nanowires for CMOS contacts. \newline \newline In collaboration with: P. Grudowski, D. Jawarani, R. Garcia, M.L. Kottke, R.B. Gregory, X.-D. Wang, D. Theodore, P. Fejes, W.J. Taylor, B.Y. Nguyen, C. Capasso, M. Raymond, D. Denning, K. Chang, R. Noble, M. Jahanbani, S. Bolton, P. Crabtree, D. Goedeke, M. Rossow, M. Chowdhury, H. Desjardins, A.Thean. [Preview Abstract] |
Wednesday, March 7, 2007 8:36AM - 8:48AM |
N39.00002: Atomistic pseudopotential simulation of nanometer sized CMOS devices Lin-Wang Wang, Jun-Wei Luo, Shu-Shen Li, Jian-Bai Xia When the size of a CMOS is shrunk to 10-20 nm, quantum mechanical effects such as individual quantum levels, quantum tunneling, and single impurity fluctuations exhibit themselves. We have developed a method to calculate the electronic structures and I-V curves of million atom CMOS devices using atomistic pseudopotential method. The electronic structure is described by the empirical pseudopotentil. The Hamilotnian is solved using the linear combination of bulk band (LCBB) [1] method in which the electron wavefunction is expanded by a set of bulk Bloch functions. Approximated formulas are developed to describe the carrier occupation and the electron current in a source-drain biased nonequilibrium system. The electrostatic potential is calculated selconsistently by solving the Poisson equation with a given boundary condition and the occupied carried density. We will present the differences between the quantum mechanical results and the traditional semiclassical results in carrier charge density, electron current, turn-on gate potential and short channel effects. [1] L.W. Wang, A. Zunger, Phys. Rev. B 59, 15806 (1999). [Preview Abstract] |
Wednesday, March 7, 2007 8:48AM - 9:00AM |
N39.00003: Interfacial engineering and electrical properties of Hf oxide films on InGaAs Lyudmila Goncharova, Ozgur Celik, Eric Garfunkel, Torgny Gustafsson, Niti Goel, Safak Sayan, Wilman Tsai The low chemical stability and poor electrical quality of native oxides, leading to Fermi level pinning, has so far prevented the fabrication of competitive InGaAs{\-}based$^{ }$devices, and made integration of InGaAs with high-$\kappa $ dielectric films a viable option. We have used atomic layer deposition to grow ultra-thin HfO$_{2}$ films on InGaAs with several surface passivation and investigated their interfacial and electrical characteristics after Al gate metal deposition using medium energy ion scattering (MEIS), x-ray photoemission (XPS), high-resolution transmission electron microscopy and electrical measurement. Structures with very thin or no interfacial oxide layer were achieved, as measured both by MEIS and XPS. Surprisingly S-passivated samples revealed that the S-containing layer does not stay at the InGaAs/HfO$_{2}$ interface but floats on top of the HfO$_{2}$ layer during deposition. Interfacial layer formation or Hf diffusion into the substrate was observed after annealing of un-passivated InGaAs devices. Electrical measurements reveal no strong change of capacitance equivalent thickness after the HfO$_{2}$ stack is annealed, although a decrease in C-V stretch out as well as in hysteresis for un-passivated capacitors is observed. [Preview Abstract] |
Wednesday, March 7, 2007 9:00AM - 9:12AM |
N39.00004: A theoretical investigation of selected silicides and germanides Manish Niranjan, Len Kleinman, Alexander A. Demkov A germanium channel field effect transistor (FET) is being considered for the next generation CMOS technology. New material system requires re-development of most elements of the device. Low resistance contacts compatible with a self aligned process have to be developed based on metal germanides, and germanides with low n- and p-type Schottky barriers (for the use in NMOS and PMOS devices) to germanium channel need to be identified. We report a comprehensive theoretical study within the framework of density functional theory of several germanides (NiGe, PtGe, YGe, Y$_{5}$Ge$_{3,}$ HfGe and HfGe$_{2})$ and compare them with monosilicides of Pt and Ni. We report bulk electronic structure and elastic properties. However, we focus on the surface properties important to thin films such as surface energy, work function and Schottky barrier height. We are able to identify thermodynamic stability fields for surface terminations resulting in work functions consistent with the low Schottky barrier requirement. Several interface structure were also considered which afford a direct evaluation of the barrier height. Germanides have complex phase diagrams, and we find \textit{ab-initio} calculations extremely useful in providing fundamental understanding of the structure-property relations between the crystal structure, chemical composition and atomic structure of the alloy/semiconductor interface on one hand and the Schottky barrier height on the other hand. [Preview Abstract] |
Wednesday, March 7, 2007 9:12AM - 9:24AM |
N39.00005: Strain-based self assembly of nanostructures for non-destructive large-scale integration E. V. Moiseeva, Y. M. Senousy, C. K. Harnett New types of curved nanostructures, departing from the plane of the substrate yet integrated with microscale contact pads, may be formed by using a strain-based assembly method. This process relies on the strain mismatch between thin films in a bilayer (in our case, metal/insulator or two different metals). By incorporating conducting and insulating materials, this method will be able to integrate active electromechanical micro- and nanostructures into microdevices, such as steerable antenna arrays, thermal nanoactuators, strain-sensitive inductors, electromagnetically resonant metamaterials, and bistable nanomechanical switches. ``Top-down'' lithography and the highly selective XeF$_{2 }$silicon dry etching process are used to obtain our released structures. The strain-based assembly technique requires no alignment step for combining nanostructures with large features, including electrical contacts and other interconnects with the outside world. We will discuss the prospects and limits for obtaining smaller thickness dimensions and lateral dimensions through electron beam lithography. [Preview Abstract] |
Wednesday, March 7, 2007 9:24AM - 9:36AM |
N39.00006: Electronic Structure and Carrier Mobility in Strain-Engineered Nanostructures Decai Yu, Yu Zhang, Ji Zang, Feng Liu Strain engineering is a major driving force to continue the performance scaling of silicon devices. However, currently strain engineering is confined in planar hetero-structures. It is anticipated that future generation of devices may employ nanostructures and new quantum principles. Here, we present theoretical studies of strain engineered nanostructures for potential device applications. Combining first-principles and finite element calculations, we analyze the electronic band structure and carrier mobility in SiGe nanotubes and Si nanomembranes that are strain-modulated by Ge quantum dots. [Preview Abstract] |
Wednesday, March 7, 2007 9:36AM - 9:48AM |
N39.00007: Experimental and Theoretical Investigation of Si(001)/Si (110) Junctions Adrian Ciucivara, Sachin Joshi, B.R. Sahu, Sanjay Banerjee, Leonard Kleinman We have observed large current asymmetries in Si(001)/Si(110) junctions where both sides are identical in all respects, except orientation. With a 280 atom GGA supercell calculation using the VASP ultrasoft pseudopotential code, we have obtained an adhesion energy of 110 meV/{\AA}$^{2}$. The covalent and dangling bonds at the interface are displayed. The Si(110) potential averaged over a (110) interior unit cell was found to be 85 meV more negative (positive for holes) than the Si(001). This offset was used in a device simulator to simulate the behavior of the junction. Qualitative agreement with the experimental I-V characteristics was obtained. We will discuss possible errors introduced in the offset by the GGA energy gap error. [Preview Abstract] |
Wednesday, March 7, 2007 9:48AM - 10:00AM |
N39.00008: Electron Transport in SiGe single-electron transistors Ian Gelfand, Jian Liu, Ya-Hong Xie, Marc Kastner It is expected that electron spins in two dimensional electron gasses (2DEGs) in SiGe heterostructures will have longer spin coherence times than GaAs 2DEGs. We have fabricated quantum point contacts and single electron transistors in this material system using palladium Schottky gates. We find that these gates can deplete the 2DEG with negligible leakage if the area of the gates is minimized, as shown by previous workers.$^{1}$ 1 K.A. Slinker et. al., New Journal of Physics 7 246 (2005) [Preview Abstract] |
Wednesday, March 7, 2007 10:00AM - 10:12AM |
N39.00009: Raman Spectroscopy Study of Uniaxial Strained SOI with SiGe Junctions Yan Du, Mehmet Ozturk, Veena Misra, Johnson Kasim, Zexiang Shen In bulk PMOSFETs, selective epitaxial Si$_{1-x}$Ge$_{x}$ junctions have been used to introduce strain into the channel for mobility enhancement purposes. Freescale has applied this idea to SOI wafers where they demonstrated that mobility enhancement is prominent for 400A partially depleted SOI PMOSFETs. But the scaling capability of this technology for very thin SOI wafers needs to be verified. In this report, we studied the impacts of body thickness and recessing on thin SOI films down to 200A. UV-raman data confirms that even without recessing, except for silicon consumed during RCA cleaning step, epitaxial Si$_{0.5}$Ge$_{0.5}$ still introduces a certain amount of strain into the channel. This is beneficial for fully depleted SOI applications, in which the ultra thin body presents challenges for RIE etching. [Preview Abstract] |
Wednesday, March 7, 2007 10:12AM - 10:24AM |
N39.00010: Low-temperature transport in Ga-implanted wires in Si S.J. Robinson, J.R. Tucker, T. Schenkel, T.-C. Shen Focused ion beams (FIBs) have potential applications in maskless device fabrication. Specifically, the narrow beam diameter and large scan range allow for the possibility of creating nanoscale interconnects (which must be highly conductive and ohmic) or even quantum devices. Here we report a low-temperature ($<$ 20 K) transport study of Ga wires created by both conventional implantation and a commercial FIB system. We find that the FIB wires yield nonlinear sheet resistances that are much higher than those of the conventional wires, which remain metallic and ohmic below 1 K. In addition, although both types of wires have positive magnetoresistance, the FIB wires show a much greater magnetic effect. The apparent conduction mechanism in our FIB wires is variable-range hopping, which transitions into Efros--Shklovskii transport and yields a Coulomb gap in $I$--$V$ measurements as the temperature is lowered. The effects of dose and annealing in conductivity will be discussed in the context of lattice defects, Ga clustering, and solid solubility. [Preview Abstract] |
Wednesday, March 7, 2007 10:24AM - 10:36AM |
N39.00011: On the Origins of Non-Exponential, Pulse Bias Induced, Capacitance Transients in Semiconductor PN Junctions Walter R. Buchwald, Peter J. Drevinsky, Christian P. Morath This work presents an analytical investigation of the temporal dependence of the pulse bias induced capacitance transient associated with an abrupt semiconductor PN junction. With minimal assumptions, Poisson's equation is used to derive a general equation for the capacitance transient which reduces to the expected exponential form only at low defect concentrations. The effect of this non-exponential transient on deep level transient spectroscopy experiments is investigated. It is shown that with increasing defect concentration, shifts in DLTS peak height maxima with respect to temperature are expected. Simulations also reveal that under certain conditions, deep level transient spectroscopy peak heights can have different magnitudes even though the defects producing the peaks have identical defect concentrations. The experimental conditions over which this general, non-exponential form, can be replaced by the purely exponential approximation are also reported. [Preview Abstract] |
Wednesday, March 7, 2007 10:36AM - 10:48AM |
N39.00012: Tuning of plasmonic resonance via modification of the shape factor of silver pillars embedded in nanopatterned silicon Jeffrey Shainline, Jimmy Xu We present a study of the feasibility of achieving ``complete resonance'' [1] in a system where silicon-on-insulator (SOI) is coupled to silver nanopillars. The SOI structure is nanopatterned using reactive ion etching through an anodized aluminium oxide etch mask to contain a periodic array of pores with radius 50nm and pitch 100nm. The resultant pores are filled with silver. The plasmonic response of the silver is studied. Attempts are made to achieve complete resonance by 1) tuning the dielectric environment of the silicon by injecting optical gain (tuning the imaginary part of the dielectric function) and by 2) modifying the shape factor of the embedded silver pillars by changing the shape of the pores in the template used for the etching. In this talk the theoretical elements will be briefly reviewed and results of recent experiments will be presented. [1] A. Smuk and N. Lawandy, Appl. Phys. B 84, 125 (2006) [Preview Abstract] |
Wednesday, March 7, 2007 10:48AM - 11:00AM |
N39.00013: Electro-Optic Films for Transmission-Mode Wavelength Demultiplexing Applications Kashma Rai, Anna Fox, Adam Fontecchio Applications for a thin-film switchable wavelength sensing device include spectral detection of telecom signals as well as chemical or biological sample identification through absorption or emission spectroscopy. The proposed device consists of configurations of holographically formed polymer dispersed liquid crystal (H-PDLC) thin film gratings for transmission-mode spectral filtering. H- PDLC films have the unique ability to selectively transmit a particular wavelength as a function of bias applied across the film. The initial configuration includes a serial wavelength sensing device formed by stacking layers of H-PDLC films. A second configuration includes parallel sensing of the spectral content by fabrication of an H-PDLC grid within a single film. The films fabricated for this study were made of a thiolene based monomer syrup with grating notches formed in the near infrared. Results of both switchable wavelength sensing systems are compared and evaluated. [Preview Abstract] |
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