Session H40: Semiconductors: Growth and Characterization
8:00 AM–10:24 AM, Tuesday, March 6, 2007
Colorado Convention Center Room: 503
Sponsoring Unit:
FIAP
Chair: Howard Branz, Energy Renewable Research Laboratory
Abstract ID: BAPS.2007.MAR.H40.8
Abstract: H40.00008 : Step Arrays on Vicinal SiC Formed by Hydrogen-Etching
9:24 AM–9:36 AM
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Abstract 
Authors:
S. Nie
(Carnegie Mellon Univ)
R.M. Feenstra
(Carnegie Mellon Univ)
Y. Ke
(Univ Pittsburgh)
R.P. Devaty
(Univ Pittsburgh)
W.J. Choyke
(Univ Pittsburgh)
G. Gu
(Sarnoff Corp)
SiC is a useful substrate for heteroepitaxy, with step arrays on the surface used to minimize defects in the film [1]. We have studied the formation of steps on SiC surfaces using H-etching at 1600\r{ }C. Both Si-face, (0001), and C-face, (000\underline {1}), surfaces are used, with miscut angles of 0, 3.5\r{ }, and 12\r{ } towards $<$1\underline {1}00$>$ or $<$11\underline {2}0$>$ directions. For H-etched surfaces it is known that steps tend to form with full unit-cell height (1.5 nm for 6H-SiC) and with step edges perpendicular to $<$1\underline {1}00$>$ [2]. Accordingly, we find that miscuts towards $<$1\underline {1}00$>$ result in ordered arrays of steps. On the Si-face step bunching is observed, with typical step heights of 4.5 nm for 12\r{ } miscut. In contrast, for the C-face, little step bunching is observed, with the surface forming well ordered arrays of single-unit-cell-high steps. For the case of miscut towards $<$11\underline {2}0$>$ the situation is more complicated, with meandering steps observed. We conclude that the C-face is most ideal as a vicinal template. Supported by NSF. \newline [1] C.D. Lee et al. MIJ-NSR \textbf{7}, 2 (2002). \newline [2] V. Ramachandran et al. JEM \textbf{27}, 308 (1998).
To cite this abstract, use the following reference: http://meetings.aps.org/link/BAPS.2007.MAR.H40.8