Bulletin of the American Physical Society
2005 APS March Meeting
Monday–Friday, March 21–25, 2005; Los Angeles, CA
Session L5: Emerging Devices and Materials for the Microelectronics Industry |
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Sponsoring Units: FIAP Chair: Alex Demkov, University of Texas, Austin Room: LACC 502B |
Tuesday, March 22, 2005 2:30PM - 3:06PM |
L5.00001: The Search for New Information Processing technologies Invited Speaker: Our society has benefited from the ‘Golden Age of Electronics’ for the last half century. The ubiquitous transistor, in its many manifestations, has enabled an explosion of capabilities in information processing, communications, and sensing that has spurred exponential growth in performance-benefit ratios. Much of the credit for this progress is due to the continued scaling of the silicon integrated circuit (IC) components and to the associated efficient fabrication processes that have made the IC affordable. There is a growing realization, from simple physics arguments, that as minimum features sizes approach the ten nanometer regime, scaling will very likely slow and eventually end. This doesn’t mean that the MOSFET will disappear, but more likely that it will need to be supplemented by other device and interconnect technologies if the exponential gains are to continue. In this talk we discuss the basis for the projected limitation of scaling of charge-based devices for logic and memory devices. We argue that a fundamental consideration for all devices, including those based on charge, relates to the capacity to manage heat generated by circuit operation. Our preference is for devices that operate at room temperature since the energy costs for cooling the devices must also be charged against the overall system energy consumption. (Cooling costs increase as a power of the difference between the ambient and the target temperature.) Therefore we seek new state variables to serve as an alternative to electrical charge for future information processing technologies. These technologies must provide the potential for sustaining exponential performance-cost benefits with time. The search must not only focus on device structures but on the underlying materials and process technologies that enable these structures. Indeed, to obtain extremely scaled CMOS, new materials and processes must also be developed. In this talk, we survey some of the candidates for replacements/supplements for/to the MOSFET and give a status report on the status of the search. We also briefly discuss the problem of design in the far nanometer regime where device variability is likely to be significant. What design constraints must be employed to ensure that manufacturing yields are high, given broad tolerance margins for the device characteristics? Variability is a growing problem in extremely scaled CMOS what is learned from these applications will likely benefit replacement technologies as well. [Preview Abstract] |
Tuesday, March 22, 2005 3:06PM - 3:42PM |
L5.00002: Physics of Modern VLSI CMOS Invited Speaker: The Integrated Circuit (IC) was invented in 1958, and modern CMOS was invented in 1980. The semiconductor physics that underlies the IC was discovered in the early part of the past century, and, by the early 60's, it was simplified and codified such that it could be used by engineers to design transistors of ever shrinking size and increasing performance. However, in the past 5-10 years, the ``engineering physics'' of the 60's is becoming increasingly inadequate. Empirical corrections are being made to allow for quantum and non-equilibrium Boltzmann transport effects. Moreover, as features in CMOS transistors reach atomic dimensions, continuum physics is no longer adequate, and devices must be designed increasingly, at the atomic level. In the past 30 years, transistor gate length has shrunk by a factor of 100X: from 10 um to 0.1 um. And it is expected to shrink by about another factor of 10X to 10 nm in the next 10-15 years. However, as transistors approach the end of scaling, the physics to design them will become increasingly complex: \begin{itemize} \item Gate oxide, which is today a few monolayers (10A) thick will be replaced with new materials with high dielectric constant. \item Metal gate electrodes will replace poly-Si, and the interface, which sets the effective work-function, needs to be understood. \item Carrier scattering in the inversion layer in the presence of increasingly high electric fields (horizontal and vertical) needs to be better understood. \item Tunneling will increasingly dominate transistor behavior. \item The discrete positioning of dopants will increasingly affect transistor performance. \item Transistors will become increasingly ballistic. \item Stress in the channel is increasing to the point where it has large impact on device performance. \item And new materials will be introduced into the Source/Drain and channel. \end{itemize} Each of these issues will be discussed, and the unresolved physics issues will be identified [Preview Abstract] |
Tuesday, March 22, 2005 3:42PM - 4:18PM |
L5.00003: Challenges for Materials to Support Emerging Research Devices Invited Speaker: The 2004 International Technology Roadmap for Semiconductors (ITRS) Emerging Research Devices Chapter has highlighted a number of emerging memory and logic devices with potential for application to future computing technologies. Digital devices operate by representing one of the 2 or more possible values of a logic ``state variable,'' and these values of the state variable are selected by the operation of the device responding to a stimulus. The operating characteristics of the device depend upon the materials and interface properties. Current state variables include: Charge transport and charge state, spin state, solid state phase, molecular charge transport state, quantum state (Qbit), flux quanta (RSFQ) field energy, and mechanical state. Devices that operate based on many of these states will need new materials, characterization and modeling techniques to measure and extract their properties at the nanometer scale. While many materials may be possible to synthesize with conventional deposition techniques, new chemical precursors or molecules may be required, but self assembly should be explored. As new nanometer scale materials are explored to fabricate these new device materials, existing metrology may need to couple with other stimuli to characterize the material and interface properties at these scales. [Preview Abstract] |
Tuesday, March 22, 2005 4:18PM - 4:54PM |
L5.00004: Novel Materials for Organic and Thin Film Electronics Invited Speaker: Pentacene is highest mobility organic semiconductor known. It forms a crystalline molecular solid that can be deposited in thin film form by either vacuum sublimation or spin-coating. In this talk I will present results of in-situ growth studies of the vapor growth of thin pentacene films on a wide variety of substrates, utilizing video-rate high resolution Low Energy Electron Microscopy (LEEM) and Photo Electron Emission Microscopy (PEEM). We find that the molecular orientation in the thin film depends directly on the electronic structure of the substrate surface (insulator, semimetal, or metal). In addition, epitaxial pentacene films can be grown on relatively weakly coupling substrates, such as semimetallic Bi, as well as insulating alkane Self-Assembled Monolayers on Si(001). The results will be illustrated with dynamic video movies of typical growth sequences. [Preview Abstract] |
Tuesday, March 22, 2005 4:54PM - 5:30PM |
L5.00005: nanoHUB.org - Towards On-Line Simulation for Materials and Nanodevices by Design Invited Speaker: Challenges in nanoelectronics are the merging notions of material and device. Device lengths have reached the nanometer scale, where material properties are defined. Detailed atomic composition such as strain, interface, doping, and size fluctuations need to be treated. Here the material science and device engineering communities meet on the common ground of quantum mechanics. Success will depend on bridging language and approach barriers between communities. The development of accepted community software will be a significant step.\newline One element of such codes is the NanoElectronic MOdeling Tool. NEMO 3-D enables the computation of strain and electronic structure in an atomistic basis for over 60 and 23 million atoms, corresponding to volumes of $(107nm)^3$ and $(77nm)^3$, respectively. NEMO 3-D runs on a serial and parallel platforms, local cluster computers as well as the NSF Teragrid. About 400,000 atoms are treated efficiently on a single 32bit CPU. NEMO uses an atomistic valence force field method (strain) and the empirical tight binding method (electronic structure). Quantitative simulations for quantum dots in the InAs/GaAs and Si/SiGe material systems have been performed. \newline The Network for Computational Nanotechnology (NCN) is in the process of developing new community and research codes for the analysis of nano-(electronic/mechanical/bio) devices. These tools are hosted on http://nanohub.org for on-line simulation use free-of-charge. Last year over 1,000 people performed about 64,000 simulations. 2,200 others viewed seminars and nanotechnology curriculum items. nanoHUB is being developed as a community resource that encourages on-line simulation, collaborations and nanotechnology education. \newline \newline Co-author: Mark S. Lundstrom [Preview Abstract] |
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