Bulletin of the American Physical Society
2005 APS March Meeting
Monday–Friday, March 21–25, 2005; Los Angeles, CA
Session J15: Focus Session: Strained Si and Other Semiconductors for Device Applications |
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Sponsoring Units: FIAP Chair: Ya-Hong Xie, UCLA Room: LACC 405 |
Tuesday, March 22, 2005 11:15AM - 11:51AM |
J15.00001: Straining Si on Insulator Invited Speaker: Transistor scaling has been the primary factor driving mainstream Si CMOS performance improvement. Approaching the fundamental limits of conventional bulk transistor scaling makes it increasingly difficult to remain on the historic scaling trend. To solve the two major scaling issues, namely increases in transistor leakage and decrease in performance improvement, new materials and device architectures are demanded. Two parallel developments in Si CMOS technology have created new opportunities in the control of channel electrostatics and the improvement of channel transport, for leakage reduction and performance enhancement. The two developments are: silicon-on-insulator (SOI) and strained channel. Due to excellent channel electrostatics, SOI transistors are considered very scalable, with their architecture scaling from partially depleted SOI for the current generation to fully depleted variety for future generations. Appropriately applied strain to the device channel can~significantly increase channel mobility, and consequently increase drive current. Both technologies can be incorporated into the CMOS device structure to significantly improve its scalability and boost its performance. In this paper, we will first describe how these two advances allow further scaling of CMOS, which include scalability improvement in SOI devices and performance enhancement by channel strain engineering. Of particular interest is the strain engineering for SOI platforms, including strained substrates and process-induced strain, leading to SiGe-on-insulator (SGOI), strained-Si-on-insulator (SSOI), and other process-induced strain techniques based on SOI substrates. We will describe the formation of such engineered substrates, implementation of the strain-engineered processing, as well as their impact on MOSFET performance. [Preview Abstract] |
Tuesday, March 22, 2005 11:51AM - 12:03PM |
J15.00002: Surface Roughness and Dislocation Distribution in Compositionally Graded Relaxed SiGe Buffer Layer with Inserted Strained Si Layers Tae-Sik Yoon, Jian Liu, Ya-Hong Xie We report the experimental investigation of surface roughness and dislocation distribution of 1 $\mu $m-thick, compositionally graded, relaxed SiGe buffer layer with a final Ge surface content of 30{\%}. Tensile-strained Si layers are inserted at various locations in the graded buffer during SiGe epitaxial growths. Slight reduction in surface roughness from about 10.3 nm to about 7.8 nm by inserting two 20 nm thick tensile-strained Si layers followed by SiGe growths. It turns out that majority of the residual surface roughness is developed during the SiGe growths on top of the topmost strain Si layer. The surface immediately after the growth of tensile strained Si is very flat with about 1.1 nm RMS roughness and without crosshatch morphology. Cross-sectional TEM shows clear signs of increased interaction between dislocation half-loops at the top surface of the strained Si layers. Our observation shows that although thin Si layers under tensile-strain are effective in reducing cross-hatch, they could in the meantime impede dislocation propagation leading to higher threading dislocation density. Considerations for an optimized scheme exploiting the flattening function of tensile-strained layers will be discussed. [Preview Abstract] |
Tuesday, March 22, 2005 12:03PM - 12:15PM |
J15.00003: Ultra-thin ambipolar germanium on insulator field effect transistors D. Kazazis, B. R. Perkins, A. Zaslavsky, E. J. Preisler, N. A. Bojarczuk, S. Guha As semiconductor technology shifts towards semiconductor-on-insulator, material combinations other than Si/SiO$_{2}$ are becoming more attractive. We will report on the transistor characteristics of ultra-thin germanium layers (less than 100 {\AA}) that have been epitaxially grown on a lattice matched epitaxial high-$\kappa $ crystalline oxide (La$_{0.27}$Y$_{0.73})_{2}$O$_{3}$, in turn grown on (111) silicon substrate. This enables the use of Ge, which has higher electron and hole mobilities than Si. Our back-gated germanium on insulator field effect transistors show good transistor characteristics, especially for the very thin layers (30 {\AA}). The devices exhibit a high I$_{on}$/I$_{off}$ ratio and they can be fully depleted and inverted, enabling both P and N channel operation in the same device. Current-voltage measurements at room and low temperature will be presented and compared with device simulations. Hall effect measurements will be used to characterize the quality of the ultra-thin Ge channels.~ [Preview Abstract] |
Tuesday, March 22, 2005 12:15PM - 12:27PM |
J15.00004: Defect-Free Strained Si-on-Insulator Structures G. M. Cohen, P.M. Mooney, V. Paruchuri, J.O. Chu, H. Chen Unlike graded SiGe buffer layers that are used for strained Si devices, free-standing Si/SiGe/Si structures that undergo elastic strain relaxation are essentially defect free and can be used to fabricate strained Si-on-insulator (SSOI) slabs suitable for SSOI MOSFETs [1-3]. We present an alternative method to form defect-free strained Si-on-Si (SSOS) or SSOI slabs by in-place bonding. An SOI wafer having a pseudomorphic SiGe layer and a Si cap layer is etched to form slabs. As the buried SiO$_2$ layer is completely etched away, the Si/SiGe/Si slabs are bonded in place to the Si substrate in the etch solution. The slabs remain bonded to the substrate by van der Waals forces when the wafer is removed from the etch bath. X-ray diffraction and AFM measurements show that the SiGe layer has relaxed elastically, i.e. no misfit dislocations are formed, and that the Si layers are under tensile strain. Subsequent annealing at high temperature forms a covalent bond. This method allows direct bonding of strained Si to Si. By suitable choice of the layer structure of the starting wafer, bonded SSOI structures can also be fabricated. The different forces involved at each stage of this in-place bonding process will be discussed. 1. G.M. Cohen, et al., Mat. Res. Soc. Symp. Proc. 768, 9 (2003). 2. P.M. Mooney, et al., Appl. Phys. Lett. 84, 1093 (2004). 3. P.M. Mooney, et al., Mat. Res. Soc. Symp. Proc. 809, 27 (2004). [Preview Abstract] |
Tuesday, March 22, 2005 12:27PM - 12:39PM |
J15.00005: Mechanical Stability of Ultra Thin Ge/Si Film on SiO$_2$:the Effect of Si/SiO$_2$ Interface Minghuang Huang, John A. Nairn, M.G. Lagally, Feng Liu We perform two-dimensional linear elastic finite element analysis to investigate mechanical stability of ultra-thin Ge/Si film grown on or bonded to SiO$_2$, using imperfect interface elements between Si and SiO$_2$ to model Si/SiO$_2$ interfacial slippage. We show that the overall composite film is stable when only the tangential slippage is allowed. But it becomes unstable when normal slippage is allowed: the coherently strained Ge island induces a large local bending of Si layer, and debonds the Si layer from the underlying SiO$_2$ forming a void at the Si/SiO$_2$ interface. Thus, the quality of Si/SiO$_2$ interface is expected to play an important role in controlling the stability of those device structures employing the strained Si/SiO$_2$ film. *This work is supported by DOE. [Preview Abstract] |
Tuesday, March 22, 2005 12:39PM - 12:51PM |
J15.00006: PECVD growth of SiGe layers for high speed devices and MEMS. Srinivasan Kannan, David Allred, Craig Taylor We will report on SiGe layers deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD; MV Systems, Colorado) for use in high speed devices, MEMS and Bolometry. Increasing the germane concentration allows the deposition temperature to be decreased, which decreases the thermal conductivity of the samples and improves their properties for bolometry. The samples were deposited up to 580$^{o}$C and doped with either diborane or phosphine. Films as deposited had predominantly $<$111$>$ texture and some $<$110$>$ texture as determined by X-ray diffraction. Annealing produced crystalline material as determined by resistivity and confirmed by X-ray diffraction with no evidence of cracking. Annealing tends to produces a variation of crystallite orientation. The crystallite sizes and orientations in the films will be discussed. Spectroscopic ellipsometry provided thickness and alloy composition. Research supported in part by NSF under grant {\#} 0073004. [Preview Abstract] |
Tuesday, March 22, 2005 12:51PM - 1:27PM |
J15.00007: The Technology of Strained Si on Insulator Invited Speaker: George Celler Scaling of MOSFET dimensions is no longer sufficient to continue performance enhancements that are expected in each subsequent silicon device generation. Improvements in charge carrier mobility are also required to stay on the Moore's curve. To achieve uniform high mobility in Si wafers, it is necessary to introduce a biaxial strain into silicon lattice. This is typically done by epitaxial growth of silicon on a virtual substrate of relaxed SiGe. Thin pseudomorphic layers of Si grow under tensile strain in order to preserve the epitaxy with a larger lattice spacing of the SiGe template. In order to take full advantage of strained Si, the film is transferred to a new substrate in such a way that there is a layer of SiO$_{2}$ between strained Si and the silicon handle wafer. Smart Cut{\texttrademark} technology, which involves wafer bonding and controlled exfoliation from the donor wafer, is the most practical way to accomplish layer transfer while preserving lattice strain. Formation of the virtual substrates is not trivial -- control and minimization of misfit dislocations are critically important. Nevertheless, strained Si on insulator (sSOI) wafers with 200 and 300mm diameter are rapidly becoming an industrial reality. Strain of $\sim $0.8{\%} is induced by growth on relaxed SiGe with 20{\%} Ge content. This can double the electron mobility in n-type transistors. Enhancing p-type devices requires higher strain values or non-standard crystal orientations. The range of strained Si thicknesses from 10-60nm allows fabrication of both fully depleted and partially depleted MOSFETs. Formation of sSOI, its properties and applications will be reviewed. [Preview Abstract] |
Tuesday, March 22, 2005 1:27PM - 1:39PM |
J15.00008: Defect reduction in HgCdTe layers by MBE growth on CdTe mesas Ramana Bommena, Chad Fulk, Jun Zhao, Tae Lee, Sivalingam Sivananthan The performance of infrared detectors is limited by the high defect density in the HgCdTe epilayers especially in the long wavelength region. This necessitates the growth of low defect density material for device fabrication. Patterned CdTe mesas have been proposed to grow low defect density HgCdTe epilayers by MBE. The reduction of defect density by growth on patterned substrates has been reported for different heteroepitaxial systems\footnote{E.A.Fitgerald \textit{et.al }`` Nucleation mechanisms and the elimination of misfit dislocations at mismatched interfaces by reduction in growth area'', J. Appl Phys.65 (6), 1989.}\footnote{S.Guha \textit{et.al} ``Defect reduction in strained InGaAs via growth on GaAs (100) substrates patterned to sub-micron dimensions'' Appl.Phys.Lett.55 (23),1990.} We report the growth of HgCdTe epilayers on CdTe mesas, fabricated from CdTe epilayers grown on silicon. A bright field mask with circular features of different sizes (ranging from 80$\mu $m-310$\mu $m) was used to fabricate mesas by contact lithography and wet isotropic etching. HgCdTe epilayers were grown in a Riber 32P MBE system. Etch pit density measurements were made on the epilayers and a reduction of EPD was observed on the mesas compared to the planar regions of the sample. This reduction of EPD could provide a breakthrough in the infrared technology. [Preview Abstract] |
Tuesday, March 22, 2005 1:39PM - 1:51PM |
J15.00009: Low Temperature Epitaxial Growth of Antimony Doped Silicon for Broadband Astronomical Charge-Coupled Devices Michael Hoenk, Jordana Blacksberg, Shouleh Nikzad, Steve Holland Future NASA missions will require exceptionally large focal plane arrays to explore the large-scale structure of the universe. High-purity, p-channel silicon CCDs provide a unique combination of high resolution, extended response in the near infrared, and improved radiation tolerance necessary for these missions. We have demonstrated low temperature growth of antimony-doped silicon on the back surface of high purity silicon charge-coupled devices (CCDs), enabling imaging at full depletion with high resolution, high quantum efficiency, and broadband response. Using molecular beam epitaxy, we were able to grow silicon layers less than 5 nm thick with an integrated dopant concentration greater than 10$^{14}$ cm$^{-2}$. Our low-temperature process kept the device temperature below 450 C at all times, enabling growth on fully-processed CCDs. We will discuss the effects of surface preparation, temperature, Sb dose, and thickness on the leakage current and quantum efficiency of these detectors. [Preview Abstract] |
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J15.00010: Dislocations in Ge/Si$_{1-x}$Ge$_x$ films: atomistic simulations and elastic-theory calculations Francesco Montalenti, Anna Marzegalli, Leo Miglio Molecular dynamics simulations based on Tersoff potentials are used to investigate 60$^\circ$ dislocation stability and mobility in compressed Ge films on Si$_{1-x}$Ge$_{x}$ [1]. For low misfit values glide dislocations appear as partials (90$^\circ$ and 30$^\circ$), separated by a stacking fault. By increasing the misfit, dissociation is no longer observed, and the core geometry becomes the perfect, Hornstra one. Elastic-theory calculations provide an explanation of the observed behavior, caused by the stress- dependent effective force acting on the two cores. Shuffle dislocations, on the other hand, behave very differently. Under high compressive strain conditions, indeed, the perfect Hornstra core is conserved during the fast gliding motion observed in the simulations. The above described misfit-dependent behavior is consistent with recent experimental results [2]. [1] A. Marzegalli, F. Montalenti, and Leo Miglio, Appl. Phys. Lett. (in press). [2] D. Chrastina et al., Thin Solid Films 459, 37 (2004). [Preview Abstract] |
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