67th Annual Gaseous Electronics Conference
Volume 59, Number 16
Sunday–Friday, November 2–7, 2014;
Raleigh, North Carolina
Session ET2: Modeling of Plasma Etching
1:30 PM–3:00 PM,
Tuesday, November 4, 2014
Room: State C
Chair: Douglas Keil, Lam Research
Abstract ID: BAPS.2014.GEC.ET2.4
Abstract: ET2.00004 : Modeling of plasma-induced damage during the etching of ultimately-scaled transistors in ULSI circuits---A model prediction of damage in three dimensional structures*
2:15 PM–2:45 PM
Preview Abstract
Abstract
Author:
Koji Eriguchi
(Kyoto University)
An increasing demand for high performance field-effect transistors (FETs)
leads to the aggressive critical dimension shrinkage and the
currently-emerging three dimensional (3D) geometry [1]. Plasma processing is
widely used also in the scaled- and 3D-FET (e.g. FinFET) manufacturing,
where precise control of the reaction on the (sidewall) surfaces is a prime
issue. In this study, damage creation mechanism during plasma
etching---plasma-induced physical damage (PPD)---was investigated in such
structures on the basis of the PPD range theory [2], atomistic simulations,
and experiments. Compared to PPD in planar FETs (e.g. Si recess [2][3]), a
stochastic modeling and atomistic simulations predicted that, during etching
of ``fins'' in a 3D-FET, the following two mechanisms are responsible for
damage creation in addition to an ion impact on the sidewall at an oblique
incident angle: 1) incoming ions penetrate into the Si substrate and undergo
scattering by Si atoms in the lateral direction even if the incident angle
is normal to the surface [4] and 2) some of Si atoms and ions sputtered at
the surface being etched impact on the sidewall with energies sufficient to
break Si-Si bonds. These straggling and sputtering processes are stochastic
and fundamental, thus, result in 3D structure damage (``fin-damage''). The
``fin-damage'' induced by straggling was modeled by the PPD range theory.
Molecular dynamics simulations clarified the mechanisms under the various
plasma conditions. Quantum mechanical calculations showed that created
defect structures play the role of a carrier trap site, which was
experimentally verified by an electrical measurement. Since they are
intrinsic natures of etching, both straggling and sputtering noted here
should be implemented to design a low-damage etching process.
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[1] I. Ferain et al., Nature 479, 310 (2011).\\[0pt]
[2] K. Eriguchi et al., Jpn. J. Appl. Phys. 49, 056203 (2010).\\[0pt]
[3] S. A. Vitale and B. A. Smith, J. Vac. Sci. Technol. B21, 2205 (2003).\\[0pt]
[4] K. Eriguchi et al., Jpn. J. Appl. Phys. 53, 03DE02 (2014).
*This work was supported in part by Grant-in-Aid for Scientific Research (B) 23360321 from JSPS and STARC project.
To cite this abstract, use the following reference: http://meetings.aps.org/link/BAPS.2014.GEC.ET2.4